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Qucs

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  Analyzed about 8 hours ago

Qucs is a integrated circuit simulator for rapid development of analog and digital circuits and wide range of simulations. DC, AC, S-parameter, noise and transient analysis are supported, mathematical equations and use of a subcircuit hierarchy are available. Digital circuit models and ... [More] simulations are supported thanks to integration with FreeHDL and Icarus Verilog. Output is may be presented with wide variety of graph and tabular charts. The package consists of two utilities: Qucs, elegant and powerfull GUI for designing and simulating circuits, with point-and-click interface, based on Qt® by Digia®. Qucsator, a command line circuit simulator. It takes a network list in a certain format as input and outputs a Qucs dataset. May also be used by applications other than [Less]

879K lines of code

8 current contributors

about 2 months since last commit

10 users on Open Hub

Low Activity
4.66667
   
0 Reviews
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Mostly written in TypeScript
Licenses: gpl
Tags analog circuit digital electronics hardware logic modeling qt simulation simulator verilog vhdl

Icarus Verilog

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  Analyzed about 21 hours ago

Icarus Verilog is an open source Verilog compiler that supports the IEEE-1364 Verilog HDL including IEEE1364-2005 plus extensions.

337K lines of code

12 current contributors

2 days since last commit

7 users on Open Hub

Moderate Activity
5.0
 
0 Reviews
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Mostly written in coq
Licenses: gpl
Tags hdl simulate simulation synthesis verilog veriloghdl

Milkymist

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  Analyzed 1 day ago

The project develops a stand-alone device in a small form factor that is capable of rendering MilkDrop-esque visuals effects in real time, with a high level of interaction with many sensors and using live audio and video streams as a base. Open source components and design tools have been developed ... [More] or used as much as possible. A system-on-chip implemented in a FPGA has been chosen for meeting this goal at the IP core level. The flexibility of the FPGA enables advanced users to modify the design, and also permits compact integration of many interfaces (MIDI, OSC, DMX512, analog sensors, video inputs), making Milkymist™ a platform of choice for the mobile VJ. The design is also highly modular and documented, making the code easy to re-use in other open source system-on-chips. [Less]

95.8K lines of code

0 current contributors

over 11 years since last commit

4 users on Open Hub

Inactive
5.0
 
0 Reviews
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Mostly written in C
Licenses: eGPL, GNU_Free_..., gpl3
Tags demo demoscene effects electronics embedded embeddedlinux embedded_systems fpga graphic hardware linux live 29 more...

VUnit HDL

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  Analyzed about 16 hours ago

VUnit is an open source unit testing framework for VHDL/SystemVerilog released under the terms of Mozilla Public License, v. 2.0. It features the functionality needed to realize continuous and automated testing of your HDL code. VUnit doesn't replace but rather complements traditional testing ... [More] methodologies by supporting a "test early and often" approach through automation. [Less]

82.9K lines of code

25 current contributors

26 days since last commit

3 users on Open Hub

Low Activity
5.0
 
0 Reviews
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Mostly written in VHDL
Licenses: mozilla_p...
Tags library logging open-source python reporting simulation systemverilog test-driven-design test-driven-development testing verification verilog 1 more...

HDMI2USB

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Claimed by TimVideos.us - Live Event S... Analyzed over 1 year ago

Hardware based on a Xilinx Spartan 6 FPGA for capturing HDMI and DVI data.

121M lines of code

13 current contributors

almost 2 years since last commit

2 users on Open Hub

Activity Not Available
0.0
 
0 Reviews
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Mostly written in coq
Licenses: apache_2
Tags camera capturecard conference digital dvi electronics firmware fpga hardware hdmi mjpeg pcb 8 more...

Verilator

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  Analyzed about 19 hours ago

Verilator converts synthesizable Verilog HDL modules into SystemC modules. This enables users with Verilog code to have a publicly available co-simulation environment. For all information, see http://www.veripool.com/verilator.html.

223K lines of code

16 current contributors

1 day since last commit

2 users on Open Hub

Very High Activity
4.0
   
0 Reviews
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Mostly written in Ruby
Licenses: Artistic_..., lgpl3
Tags systemc verilog

Electronic Design Automation Abstraction (EDA²)

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  Analyzed about 13 hours ago

40.1K lines of code

0 current contributors

about 1 month since last commit

2 users on Open Hub

Very Low Activity
0.0
 
0 Reviews
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Mostly written in Python
Licenses: No declared licenses
Tags eda implementation layers simulation stack synthesis verilog vhdl

opbasm

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  Analyzed about 17 hours ago

Opbasm is a free cross-platform assembler for the PicoBlaze-3 (PB3) and PicoBlaze-6 (PB6) microcontrollers provided by Xilinx. It will run readily on any platform with a Python interpreter. Opbasm provides a better performing solution to assembling PicoBlaze code without resorting to DOS or Windows ... [More] emulation to run the native KCPSM assemblers. [Less]

9.59K lines of code

2 current contributors

about 2 years since last commit

1 users on Open Hub

Inactive
5.0
 
0 Reviews
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Mostly written in Python
Licenses: mit
Tags 8-bit assembler fpga kcpsm picoblaze processor soft-core verilog vhdl xilinx

SIMULinho

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  Analyzed about 1 hour ago

Simulador integrado iVerilog com interface QT, permite visualizar internamente e controlar a simulação do RISCuinho usando iVerilog

110 lines of code

0 current contributors

over 4 years since last commit

1 users on Open Hub

Inactive
0.0
 
0 Reviews
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Mostly written in C++
Licenses: No declared licenses
Tags fpga ieee1394 iverlog simulation synthesiser verilog

FPGALink

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  Analyzed about 12 hours ago

The aim of the FPGALink project is to provide a hardware abstraction layer for hardware involving an FPGA connected to a computer over USB, to abstract core functionality like FPGA-programming and subsequent host-FPGA communication. It doesn't matter whether the hardware uses an AVR, an FX2LP or an ... [More] ARM-based micro for its USB interface. It doesn't matter whether the FPGA is from Xilinx or Altera or Lattice or whomever. It doesn't matter whether the interface between them is a fast 43MiB/s parallel synchronous interface, a much slower EPP interface or some sort of USART connection. The cross-platform, cross-language host-side API is the same, and the FPGA-side (VHDL or Verilog) FIFO interface is the same, so you can easily port your design to a new FPGA devkit or to your own custom PCB. [Less]

32.8K lines of code

0 current contributors

over 7 years since last commit

1 users on Open Hub

Inactive
0.0
 
0 Reviews
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Mostly written in C
Licenses: GNU_Gener..., gpl3_or_l..., lgpv3_or_...
Tags altera avr electronics fpga fx2lp jtag lattice linux lpc macosx usb verilog 3 more...