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Qucs
Analyzed 1 day ago
Qucs is a integrated circuit simulator for rapid development of analog and digital circuits and wide range of simulations.
DC, AC, S-parameter, noise and transient analysis are supported, mathematical equations and use of a subcircuit hierarchy are available. Digital circuit models and
Licenses:
gpl
Icarus Verilog
Analyzed 1 day ago
Icarus Verilog is an open source Verilog compiler that supports the IEEE-1364 Verilog HDL including IEEE1364-2005 plus extensions.
Milkymist
Analyzed about 19 hours ago
The project develops a stand-alone device in a small form factor that is capable of rendering MilkDrop-esque visuals effects in real time, with a high level of interaction with many sensors and using live audio and video streams as a base.
Open source components and design tools have been developed
Licenses:
eGPL, GNU_Free_..., gpl3
VUnit HDL
Analyzed about 13 hours ago
VUnit is an open source unit testing framework for VHDL/SystemVerilog released under the terms of Mozilla Public License, v. 2.0. It features the functionality needed to realize continuous and automated testing of your HDL code. VUnit doesn't replace but rather complements traditional testing
Licenses:
mozilla_p...
HDMI2USB
H
Claimed by TimVideos.us - Live Event S... Analyzed 4 months ago
Hardware based on a Xilinx Spartan 6 FPGA for capturing HDMI and DVI data.
Licenses:
apache_2
Electronic Design Automation Abstraction (EDA²)
Analyzed about 17 hours ago
Licenses:
No declared licenses
opbasm
O
Analyzed 1 day ago
Opbasm is a free cross-platform assembler for the PicoBlaze-3 (PB3) and PicoBlaze-6 (PB6) microcontrollers provided by Xilinx. It will run readily on any platform with a Python interpreter. Opbasm provides a better performing solution to assembling PicoBlaze code without resorting to DOS or Windows
SIMULinho
S
Analyzed about 11 hours ago
Simulador integrado iVerilog com interface QT, permite visualizar internamente e controlar a simulação do RISCuinho usando iVerilog
Licenses:
No declared licenses
Verilator
V
No analysis available
Verilator converts synthesizable Verilog HDL modules into SystemC modules. This enables users with Verilog code to have a publicly available co-simulation environment. For all information, see http://www.veripool.com/verilator.html.
Mostly written in language not available
Licenses:
Artistic_..., lgpl3
FPGALink
Analyzed 1 day ago
The aim of the FPGALink project is to provide a hardware abstraction layer for hardware involving an FPGA connected to a computer over USB, to abstract core functionality like FPGA-programming and subsequent host-FPGA communication. It doesn't matter whether the hardware uses an AVR, an FX2LP or an
Licenses:
GNU_Gener..., gpl3_or_l..., lgpv3_or_...