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Analyzed about 12 hours ago. based on code collected 1 day ago.

Project Summary

The aim of the FPGALink project is to provide a hardware abstraction layer for hardware involving an FPGA connected to a computer over USB, to abstract core functionality like FPGA-programming and subsequent host-FPGA communication. It doesn't matter whether the hardware uses an AVR, an FX2LP or an ARM-based micro for its USB interface. It doesn't matter whether the FPGA is from Xilinx or Altera or Lattice or whomever. It doesn't matter whether the interface between them is a fast 43MiB/s parallel synchronous interface, a much slower EPP interface or some sort of USART connection. The cross-platform, cross-language host-side API is the same, and the FPGA-side (VHDL or Verilog) FIFO interface is the same, so you can easily port your design to a new FPGA devkit or to your own custom PCB.

Tags

altera avr electronics fpga fx2lp jtag lattice linux lpc macosx usb verilog vhdl windows xilinx

In a Nutshell, FPGALink...

GNU General Public License v2.0 only
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Commercial Use

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These details are provided for information only. No information here is legal advice and should not be used as such.

GNU General Public License v3.0 or later
Permitted

Commercial Use

Modify

Distribute

Place Warranty

Use Patent Claims

Forbidden

Sub-License

Hold Liable

Required

Distribute Original

Disclose Source

Include Copyright

State Changes

Include License

Include Install Instructions

These details are provided for information only. No information here is legal advice and should not be used as such.

GNU Lesser General Public License v3.0 or later
Permitted

Commercial Use

Modify

Distribute

Place Warranty

Use Patent Claims

Forbidden

Sub-License

Hold Liable

Required

Distribute Original

Disclose Source

Include Copyright

State Changes

Include License

Include Install Instructions

These details are provided for information only. No information here is legal advice and should not be used as such.

Project Security

Vulnerabilities per Version ( last 10 releases )

There are no reported vulnerabilities

Project Vulnerability Report

Security Confidence Index

Poor security track-record
Favorable security track-record

Vulnerability Exposure Index

Many reported vulnerabilities
Few reported vulnerabilities

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About Project Security

Languages

C
43%
VHDL
21%
C++
13%
10 Other
23%

30 Day Summary

Aug 25 2022 — Sep 24 2022

12 Month Summary

Sep 24 2021 — Sep 24 2022

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