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FPGALink

  Analyzed about 20 hours ago

The aim of the FPGALink project is to provide a hardware abstraction layer for hardware involving an FPGA connected to a computer over USB, to abstract core functionality like FPGA-programming and subsequent host-FPGA communication. It doesn't matter whether the hardware uses an AVR, an FX2LP or an ... [More] ARM-based micro for its USB interface. It doesn't matter whether the FPGA is from Xilinx or Altera or Lattice or whomever. It doesn't matter whether the interface between them is a fast 43MiB/s parallel synchronous interface, a much slower EPP interface or some sort of USART connection. The cross-platform, cross-language host-side API is the same, and the FPGA-side (VHDL or Verilog) FIFO interface is the same, so you can easily port your design to a new FPGA devkit or to your own custom PCB. [Less]

32.8K lines of code

0 current contributors

about 6 years since last commit

1 users on Open Hub

Inactive
0.0
 
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Licenses: GNU_Gener..., gpl3_or_l..., lgpv3_or_...

PicoBlaze-Library

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  Analyzed about 19 hours ago

The PicoBlaze-Library offers several PicoBlaze devices and code routines to extend a common PicoBlaze environment to a little System on a Chip (SoC or SoFPGA).

15.6K lines of code

0 current contributors

over 8 years since last commit

1 users on Open Hub

Inactive
5.0
 
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PoC-Library

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  Analyzed about 7 hours ago

IP Core Library - Published and maintained by the Chair for VLSI Design, Diagnostics and Architecture, Faculty of Computer Science, Technische Universität Dresden, Germany

52.9K lines of code

2 current contributors

over 4 years since last commit

1 users on Open Hub

Inactive
5.0
 
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pyIPCMI

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  Analyzed about 8 hours ago

A Python-based IP Core Management Infrastructure.

16.7K lines of code

1 current contributors

over 4 years since last commit

1 users on Open Hub

Inactive
0.0
 
I Use This