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Analyzed about 14 hours ago. based on code collected about 14 hours ago.

Project Summary

IP Core Library - Published and maintained by the Chair for VLSI Design, Diagnostics and Architecture, Faculty of Computer Science, Technische Universität Dresden, Germany

Tags

aldec altera arithmetic cross-platform fifo fpga i2c ipcore lattice library mentorgraphics open-source python3 sdram simulation toolchain verification vga vhdl xilinx

Apache License 2.0
Permitted

Commercial Use

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Private Use

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Required

Include Copyright

State Changes

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These details are provided for information only. No information here is legal advice and should not be used as such.

Project Security

Vulnerabilities per Version ( last 10 releases )

There are no reported vulnerabilities

Project Vulnerability Report

Security Confidence Index

Poor security track-record
Favorable security track-record

Vulnerability Exposure Index

Many reported vulnerabilities
Few reported vulnerabilities

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About Project Security

Languages

VHDL
85%
11 Other
15%

30 Day Summary

Oct 22 2025 — Nov 21 2025

12 Month Summary

Nov 21 2024 — Nov 21 2025