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PoC-Library

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  Analyzed 1 day ago

IP Core Library - Published and maintained by the Chair for VLSI Design, Diagnostics and Architecture, Faculty of Computer Science, Technische Universität Dresden, Germany

52.9K lines of code

2 current contributors

about 4 years since last commit

1 users on Open Hub

Inactive
5.0
 
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pyIPCMI

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  Analyzed 1 day ago

A Python-based IP Core Management Infrastructure.

16.7K lines of code

1 current contributors

over 4 years since last commit

1 users on Open Hub

Inactive
0.0
 
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cextools

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  Analyzed about 21 hours ago

Some small command line programs and a file parser for Concept Explorer written in C++. Currently features include: Converters from concept explorer into PDF, PostScript, SVG and PovRay, a modified 3D Freese layout.

6.27K lines of code

0 current contributors

over 10 years since last commit

1 users on Open Hub

Inactive
0.0
 
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sailfish-cfd

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  Analyzed about 14 hours ago

Sailfish is an Open Source fluid dynamics solver for CUDA devices. It uses the Lattice Boltzmann method to simulate incompressible and weakly compressible flows in 2D and 3D. The project uses Python to maintain a rapid pace of development and high level of code readability. pycuda and numpy ... [More] allow it to achieve high performance without compromising the flexibility offered by Python. [Less]

42.5K lines of code

0 current contributors

over 4 years since last commit

1 users on Open Hub

Inactive
0.0
 
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FPGALink

  Analyzed about 5 hours ago

The aim of the FPGALink project is to provide a hardware abstraction layer for hardware involving an FPGA connected to a computer over USB, to abstract core functionality like FPGA-programming and subsequent host-FPGA communication. It doesn't matter whether the hardware uses an AVR, an FX2LP or an ... [More] ARM-based micro for its USB interface. It doesn't matter whether the FPGA is from Xilinx or Altera or Lattice or whomever. It doesn't matter whether the interface between them is a fast 43MiB/s parallel synchronous interface, a much slower EPP interface or some sort of USART connection. The cross-platform, cross-language host-side API is the same, and the FPGA-side (VHDL or Verilog) FIFO interface is the same, so you can easily port your design to a new FPGA devkit or to your own custom PCB. [Less]

32.8K lines of code

0 current contributors

about 6 years since last commit

1 users on Open Hub

Inactive
0.0
 
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Licenses: GNU_Gener..., gpl3_or_l..., lgpv3_or_...

tmLQCD

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  Analyzed about 6 hours ago

tmLQCD is a freely available software suite providing a set of tools to be used in lattice QCD simulations. This is mainly a (P)HMC implementation for Wilson and Wilson twisted mass fermions and inverter for different versions of the Dirac operator. The code is fully parallelised and ships with ... [More] optimisations for various modern architectures, such as commodity PC clusters and the Blue Gene family. [Less]

105K lines of code

5 current contributors

7 days since last commit

0 users on Open Hub

Moderate Activity
0.0
 
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NTRU

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  Analyzed about 17 hours ago

This project provides an implementation of the NTRU public key cryptosystem in Java. It consists of NTRUEncrypt, an encryption scheme; and NTRUSign, a signature scheme. Both algorithms are higher performance than RSA and ECC, and are considered resistant to quantum computers.

7.26K lines of code

0 current contributors

about 4 years since last commit

0 users on Open Hub

Inactive
0.0
 
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