UrJTAG aims to create an enhanced, modern tool for communicating over JTAG with flash chips, CPUs, and many more. It takes on the well proven openwince jtag tools code. Future plans include conversion of the code base into a library that can be used with other applications. A flexible remote
... [More] communication protocol that can be used over almost any type of serial link (including TCP/IP) is currently being defined. [Less]
The aim of the FPGALink project is to provide a hardware abstraction layer for hardware involving an FPGA connected to a computer over USB, to abstract core functionality like FPGA-programming and subsequent host-FPGA communication. It doesn't matter whether the hardware uses an AVR, an FX2LP or an
... [More] ARM-based micro for its USB interface. It doesn't matter whether the FPGA is from Xilinx or Altera or Lattice or whomever. It doesn't matter whether the interface between them is a fast 43MiB/s parallel synchronous interface, a much slower EPP interface or some sort of USART connection. The cross-platform, cross-language host-side API is the same, and the FPGA-side (VHDL or Verilog) FIFO interface is the same, so you can easily port your design to a new FPGA devkit or to your own custom PCB. [Less]
A simple jtag programming tool that has been verified on a variety of Xilinx Series7 platforms.
It also supports interacting with the logic and gathering traces via BscanE2 primitives.
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