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OpenOCD

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  Analyzed about 4 hours ago

The "Open On-Chip Debugger" provides JTAG access from GDB (or directly with TCL scripts) to processors with ARM and MIPS based cores.

275K lines of code

56 current contributors

about 1 month since last commit

32 users on Open Hub

High Activity
4.875
   
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UrJTAG

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  Analyzed 1 day ago

UrJTAG aims to create an enhanced, modern tool for communicating over JTAG with flash chips, CPUs, and many more. It takes on the well proven openwince jtag tools code. Future plans include conversion of the code base into a library that can be used with other applications. A flexible remote ... [More] communication protocol that can be used over almost any type of serial link (including TCP/IP) is currently being defined. [Less]

76.4K lines of code

0 current contributors

about 7 years since last commit

4 users on Open Hub

Inactive
5.0
 
I Use This
Licenses: No declared licenses

FPGALink

  Analyzed about 15 hours ago

The aim of the FPGALink project is to provide a hardware abstraction layer for hardware involving an FPGA connected to a computer over USB, to abstract core functionality like FPGA-programming and subsequent host-FPGA communication. It doesn't matter whether the hardware uses an AVR, an FX2LP or an ... [More] ARM-based micro for its USB interface. It doesn't matter whether the FPGA is from Xilinx or Altera or Lattice or whomever. It doesn't matter whether the interface between them is a fast 43MiB/s parallel synchronous interface, a much slower EPP interface or some sort of USART connection. The cross-platform, cross-language host-side API is the same, and the FPGA-side (VHDL or Verilog) FIFO interface is the same, so you can easily port your design to a new FPGA devkit or to your own custom PCB. [Less]

32.8K lines of code

0 current contributors

about 6 years since last commit

1 users on Open Hub

Inactive
0.0
 
I Use This
Licenses: GNU_Gener..., gpl3_or_l..., lgpv3_or_...

fpgajtag

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  Analyzed about 19 hours ago

A simple jtag programming tool that has been verified on a variety of Xilinx Series7 platforms. It also supports interacting with the logic and gathering traces via BscanE2 primitives.

3.52K lines of code

0 current contributors

almost 2 years since last commit

1 users on Open Hub

Very Low Activity
0.0
 
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msp430dll

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  Analyzed about 4 hours ago

MSP430DLL (Python wrapper for msp430.dll).

1.29K lines of code

1 current contributors

about 5 years since last commit

0 users on Open Hub

Inactive
0.0
 
I Use This
Licenses: No declared licenses