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connectal

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  Analyzed about 10 hours ago

Connectal makes it easy to develop hardware-accelerated software using FPGAs. Define the hardware/software interface, write the HDL, write the software, build it and test it. No drivers required! Connectal currently supports Xilinx Virtex, Kintex, and especially Zynq FPGAs as well as Altera ... [More] FPGAs. We develop our hardware using Bluespec System Verilog. [Less]

70.8K lines of code

3 current contributors

5 months since last commit

2 users on Open Hub

Very Low Activity
0.0
 
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fpgajtag

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  Analyzed about 2 hours ago

A simple jtag programming tool that has been verified on a variety of Xilinx Series7 platforms. It also supports interacting with the logic and gathering traces via BscanE2 primitives.

3.52K lines of code

0 current contributors

almost 2 years since last commit

1 users on Open Hub

Very Low Activity
0.0
 
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fpgamake

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  Analyzed about 14 hours ago

fpgamake generates make files enabling separate synthesis, placement, and routing of designs for Xilinx Virtex, Kintex, and Zynq FPGAs.

1.8K lines of code

0 current contributors

almost 2 years since last commit

0 users on Open Hub

Very Low Activity
0.0
 
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CTU CAN FD IP Core

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  Analyzed 3 months ago

Open-source CAN with Flexible Data-rate IP Core implemented in VHDL and associated SocketCAN Linux kernel driver. Project has been started at Czech Technical University in Prague. The core Integration with Zynq-7000 system: https://gitlab.fel.cvut.cz/canbus/zynq/zynq-can-sja1000-top ... [More] Integration with Intel EP4CGX15 based DB4CGX15 PCIe board: https://gitlab.fel.cvut.cz/canbus/pcie-ctu_can_fd [Less]

290K lines of code

0 current contributors

3 months since last commit

0 users on Open Hub

Activity Not Available
0.0
 
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Licenses: Commercial, GPL2, mit