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VUnit HDL
Analyzed 1 day ago
VUnit is an open source unit testing framework for VHDL/SystemVerilog released under the terms of Mozilla Public License, v. 2.0. It features the functionality needed to realize continuous and automated testing of your HDL code. VUnit doesn't replace but rather complements traditional testing
Licenses:
mozilla_p...
UVE-project
Analyzed about 3 hours ago
The UVE project creates software that automatically generates verification testbenches (TB) written in SystemVerilog (SV) integrating the UVM methodology.
UVE makes the development of verification environments rapid and simple. The generated TB performs random actions on the DUV. It provides a
Licenses:
apache_2, AGPL3_or_...
Verilog Perl
V
Analyzed 12 months ago
The Verilog-Perl distribution provides Perl preprocessing, parsing and utilities for the Verilog Language. It is also available from CPAN under the Verilog:: namespace.
Licenses:
No declared licenses
verible
V
Analyzed 1 day ago
Verible provides a SystemVerilog parser, style-linter, and formatter.
Licenses:
apache_2
pySVModel
P
Analyzed about 11 hours ago
An abstract language model of SystemVerilog (incl. Verilog) written in Python.
Licenses:
apache_2