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VUnit HDL

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  Analyzed about 12 hours ago

VUnit is an open source unit testing framework for VHDL/SystemVerilog released under the terms of Mozilla Public License, v. 2.0. It features the functionality needed to realize continuous and automated testing of your HDL code. VUnit doesn't replace but rather complements traditional testing ... [More] methodologies by supporting a "test early and often" approach through automation. [Less]

79.3K lines of code

25 current contributors

28 days since last commit

3 users on Open Hub

Moderate Activity
5.0
 
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UVE-project

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  Analyzed 1 day ago

The UVE project creates software that automatically generates verification testbenches (TB) written in SystemVerilog (SV) integrating the UVM methodology. UVE makes the development of verification environments rapid and simple. The generated TB performs random actions on the DUV. It provides a ... [More] graphical user interface, a code generator, compilation scripts and a library of verification IPs (VIP). One of the main innovations of UVE is a list of TODOs in the TB code to help finalizing the TB. This is especially useful for developers not familiar with SV and/or UVE, but also experienced developers profit from that task list. The graphical interface lets the user observe and navigate the structure of the generated testbench. Simulation is launched directly from the tool. [Less]

923K lines of code

1 current contributors

almost 6 years since last commit

1 users on Open Hub

Inactive
0.0
 
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Licenses: apache_2, AGPL3_or_...

Verilog Perl

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  Analyzed about 5 hours ago

The Verilog-Perl distribution provides Perl preprocessing, parsing and utilities for the Verilog Language. It is also available from CPAN under the Verilog:: namespace.

17.7K lines of code

1 current contributors

3 months since last commit

0 users on Open Hub

Very Low Activity
0.0
 
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Licenses: No declared licenses

verible

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  Analyzed about 1 hour ago

Verible provides a SystemVerilog parser, style-linter, and formatter.

166K lines of code

0 current contributors

3 days since last commit

0 users on Open Hub

High Activity
0.0
 
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pySVModel

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  Analyzed 7 minutes ago

An abstract language model of SystemVerilog (incl. Verilog) written in Python.

414 lines of code

0 current contributors

8 months since last commit

0 users on Open Hub

Very Low Activity
0.0
 
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