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pyVHDLModel

Analyzed about 16 hours ago

An abstract language model of VHDL written in Python.

6.61K lines of code

0 current contributors

3 months since last commit

2 users on Open Hub

Very Low Activity

I Use This

Licenses: apache_2

Analyzed 1 day ago

An abstract language model of SystemVerilog (incl. Verilog) written in Python.

414 lines of code

0 current contributors

8 months since last commit

0 users on Open Hub

Very Low Activity

I Use This

Licenses: apache_2