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pyVHDLModel

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  Analyzed 1 day ago

An abstract language model of VHDL written in Python.

7.83K lines of code

0 current contributors

23 days since last commit

2 users on Open Hub

Moderate Activity
5.0
 
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pySVModel

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  Analyzed about 7 hours ago

An abstract language model of SystemVerilog (incl. Verilog) written in Python.

800 lines of code

0 current contributors

23 days since last commit

0 users on Open Hub

Very Low Activity
0.0
 
I Use This