This project has been reported as a duplicate of Electronic Design Automation Abstraction (EDA²). This project will be deleted upon review by an Open Hub administrator.
An abstract language model of SystemVerilog (incl. Verilog) written in Python.
Commercial Use
Modify
Distribute
Place Warranty
Sub-License
Private Use
Use Patent Claims
Hold Liable
Use Trademarks
Include Copyright
State Changes
Include License
Include Notice
These details are provided for information only. No information here is legal advice and should not be used as such.
There are no reported vulnerabilities
30 Day SummaryMar 18 2024 — Apr 17 2024
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12 Month SummaryApr 17 2023 — Apr 17 2024
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