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Analyzed about 12 hours ago. based on code collected 1 day ago.

Project Summary

Qucs is a integrated circuit simulator for rapid development of analog and digital circuits and wide range of simulations.

DC, AC, S-parameter, noise and transient analysis are supported, mathematical equations and use of a subcircuit hierarchy are available. Digital circuit models and simulations are supported thanks to integration with FreeHDL and Icarus Verilog.
Output is may be presented with wide variety of graph and tabular charts.

The package consists of two utilities:
Qucs, elegant and powerfull GUI for designing and simulating circuits, with point-and-click interface, based on Qt® by Digia®.
Qucsator, a command line circuit simulator. It takes a network list in a certain format as input and outputs a Qucs dataset. May also be used by applications other than

Tags

analog circuit digital electronics hardware logic modeling qt simulation simulator verilog vhdl

GNU General Public License v2.0 or later
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These details are provided for information only. No information here is legal advice and should not be used as such.

Project Security

Vulnerabilities per Version ( last 10 releases )

There are no reported vulnerabilities

Project Vulnerability Report

Security Confidence Index

Poor security track-record
Favorable security track-record

Vulnerability Exposure Index

Many reported vulnerabilities
Few reported vulnerabilities

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About Project Security

Languages

TypeScript
63%
C++
21%
TeX/LaTeX
10%
13 Other
6%

30 Day Summary

Nov 4 2023 — Dec 4 2023

12 Month Summary

Dec 4 2022 — Dec 4 2023

Ratings

3 users rate this project:
4.66667
   
4.7/5.0
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