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Analyzed about 15 hours ago. based on code collected 1 day ago.

Project Summary

Icarus Verilog is an open source Verilog compiler that supports the IEEE-1364 Verilog HDL including IEEE1364-2005 plus extensions.

Tags

hdl simulate simulation synthesis verilog veriloghdl

In a Nutshell, Icarus Verilog...

GNU General Public License v2.0 or later
Permitted

Commercial Use

Modify

Distribute

Place Warranty

Forbidden

Sub-License

Hold Liable

Required

Distribute Original

Disclose Source

Include Copyright

State Changes

Include License

These details are provided for information only. No information here is legal advice and should not be used as such.

Project Security

Vulnerabilities per Version ( last 10 releases )

There are no reported vulnerabilities

Project Vulnerability Report

Security Confidence Index

Poor security track-record
Favorable security track-record

Vulnerability Exposure Index

Many reported vulnerabilities
Few reported vulnerabilities

Did You Know...

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    in 2016, 47% of companies did not have formal process in place to track OS code
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    data presented on the Open Hub is available through our API
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    learn about Open Hub updates and features on the Open Hub blog
About Project Security

Languages

coq
40%
C++
37%
C
19%
7 Other
4%

30 Day Summary

Sep 4 2026 — Oct 4 2026

12 Month Summary

Oct 4 2025 — Oct 4 2026
  • 610 Commits
    Up + 496 (435%) from previous 12 months
  • 17 Contributors
    Up + 5 (41%) from previous 12 months

Ratings

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