7
I Use This!
Moderate Activity
Analyzed about 17 hours ago. based on code collected about 20 hours ago.

Project Summary

Icarus Verilog is an open source Verilog compiler that supports the IEEE-1364 Verilog HDL including IEEE1364-2005 plus extensions.

Tags

hdl simulate simulation synthesis verilog veriloghdl

GNU General Public License v2.0 or later
Permitted

Commercial Use

Modify

Distribute

Place Warranty

Forbidden

Sub-License

Hold Liable

Required

Distribute Original

Disclose Source

Include Copyright

State Changes

Include License

These details are provided for information only. No information here is legal advice and should not be used as such.

Project Security

Vulnerabilities per Version ( last 10 releases )

There are no reported vulnerabilities

Project Vulnerability Report

Security Confidence Index

Poor security track-record
Favorable security track-record

Vulnerability Exposure Index

Many reported vulnerabilities
Few reported vulnerabilities

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About Project Security

Languages

coq
39%
C++
37%
C
20%
7 Other
4%

30 Day Summary

Nov 6 2023 — Dec 6 2023

12 Month Summary

Dec 6 2022 — Dec 6 2023
  • 370 Commits
    Down -200 (35%) from previous 12 months
  • 17 Contributors
    Up + 1 (6%) from previous 12 months