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Verilator
V
Analyzed about 13 hours ago
Verilator converts synthesizable Verilog HDL modules into SystemC modules. This enables users with Verilog code to have a publicly available co-simulation environment. For all information, see http://www.veripool.com/verilator.html.
Licenses:
Artistic_..., lgpl3
SoCLib
No analysis available
SoCLib is a library of pluggable SystemC cycle-accurate and transaction-level components. The library contains many types of models: processor cores (MIPS32, PPC405, ARM-v6k, Nios2, MicroBlaze, lm32, etc.), memory types, devices (block device, UART, frame buffer, etc.) and network-on-chip models.
Mostly written in language not available
Licenses:
gpl, lgpl21_or...
SystemC
Analyzed about 2 hours ago
SystemC addresses the need for a system design and verification language that spans hardware and software. It is a language built as an ANSI C++ class library created for design and verification. Users worldwide are applying SystemC to system-level modeling, abstract analog/mixed-signal modeling
Licenses:
apache_2
NOCEXplore
N
Analyzed about 7 hours ago
NOCEXplore is a Network-on-Chip design exploration tool based on SystemC. It includes libraries and executables for easy and fast upgradeable NoC models and a set of shell scripts.
Licenses:
No declared licenses