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FPGALink

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  Analyzed about 4 hours ago

The aim of the FPGALink project is to provide a hardware abstraction layer for hardware involving an FPGA connected to a computer over USB, to abstract core functionality like FPGA-programming and subsequent host-FPGA communication. It doesn't matter whether the hardware uses an AVR, an FX2LP or an ... [More] ARM-based micro for its USB interface. It doesn't matter whether the FPGA is from Xilinx or Altera or Lattice or whomever. It doesn't matter whether the interface between them is a fast 43MiB/s parallel synchronous interface, a much slower EPP interface or some sort of USART connection. The cross-platform, cross-language host-side API is the same, and the FPGA-side (VHDL or Verilog) FIFO interface is the same, so you can easily port your design to a new FPGA devkit or to your own custom PCB. [Less]

32.8K lines of code

0 current contributors

over 7 years since last commit

1 users on Open Hub

Inactive
0.0
 
0 Reviews
I Use This
Mostly written in C
Licenses: GNU_Gener..., gpl3_or_l..., lgpv3_or_...
Tags altera avr electronics fpga fx2lp jtag lattice linux lpc macosx usb verilog 3 more...

VHDLTest

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  Analyzed about 7 hours ago

VHDL Test Runner Tool

3.77K lines of code

0 current contributors

3 months since last commit

1 users on Open Hub

Very Low Activity
0.0
 
0 Reviews
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Mostly written in C#
Licenses: mit
Tags fpga testingtool vhdl

schifra

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  Analyzed 1 day ago

Schifra is a very robust, highly optimized and extremely configurable Reed-Solomon error correcting code library for both software and IP core based applications with implementations in C++ and VHDL. Schifra supports standard, shortened and punctured Reed-Solomon codes. It also has support for ... [More] stacked product codes and interleaving. General Features * Errors and Erasures * Supported Symbol Sizes - 2 to 32 bits * Variable Code Block Length * User defined primitive polynomial and finite field * Accurate and Validated Reed-Solomon Codecs - Complete combinatorial errors and erasures unit testing [Less]

7.44K lines of code

1 current contributors

over 5 years since last commit

1 users on Open Hub

Inactive
5.0
 
0 Reviews
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Mostly written in C++
Licenses: gpl
Tags bch c++ circ code correcting cplusplus crc dvb ecc error errorcorrecting error-handling 7 more...

UVVM

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  Analyzed about 19 hours ago

The VVC Framework is a VHDL Verification Component system that allows multiple interfaces on a DUT to be stimulated/handled simultaneously in a very structured manner, and controlled by a very simple to understand software like a test sequencer. VVC Framework is unique as an open source VHDL ... [More] approach to building a structured testbench architecture using Verification components and a simple protocol to access these. As an example a simple command like uart_expect(UART_VVCT, my_data), or axilite_write(AXILITE_VVCT, my_addr, my_data, my_message) will automatically tell the respective VVC (for UART or AXI-Lite) to execute the uart_receive() or axilite_write() BFM respectively. [Less]

210K lines of code

3 current contributors

2 days since last commit

1 users on Open Hub

Low Activity
4.0
   
0 Reviews
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Mostly written in VHDL
Licenses: mit
Tags logging reporting simulation testing verification vhdl

opbasm

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  Analyzed about 9 hours ago

Opbasm is a free cross-platform assembler for the PicoBlaze-3 (PB3) and PicoBlaze-6 (PB6) microcontrollers provided by Xilinx. It will run readily on any platform with a Python interpreter. Opbasm provides a better performing solution to assembling PicoBlaze code without resorting to DOS or Windows ... [More] emulation to run the native KCPSM assemblers. [Less]

9.59K lines of code

2 current contributors

almost 2 years since last commit

1 users on Open Hub

Very Low Activity
5.0
 
0 Reviews
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Mostly written in Python
Licenses: mit
Tags 8-bit assembler fpga kcpsm picoblaze processor soft-core verilog vhdl xilinx

Kactus2

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  No analysis available

Kactus2 is the first graphical open source IP-XACT toolset to design embedded products, especially FPGA-based MP-SoCs. It provides easier IP reusabilility and practical HW/SW abstraction for easier application SW development.

0 lines of code

7 current contributors

0 since last commit

1 users on Open Hub

Activity Not Available
0.0
 
0 Reviews
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Mostly written in language not available
Licenses: GPL2
Tags codesign embedded_systems fpga ip-xact mcapi product_data_management systemdesign vhdl

cocotb

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  Analyzed about 1 hour ago

Coroutine Co-simulation Test Bench

41K lines of code

39 current contributors

1 day since last commit

1 users on Open Hub

High Activity
3.0
   
0 Reviews
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Mostly written in Python
Licenses: BSD-3-Clause
Tags framework python simulation verification vhdl

pyIPCMI

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  Analyzed about 7 hours ago

A Python-based IP Core Management Infrastructure.

16.7K lines of code

1 current contributors

almost 6 years since last commit

1 users on Open Hub

Inactive
0.0
 
0 Reviews
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Mostly written in Python
Licenses: apache_2
Tags aldec altera cross-platform intel intelfpga ipcore ipxact lattice mentorgraphics open-source poc python3 4 more...

PicoBlaze-Library

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  Analyzed about 24 hours ago

The PicoBlaze-Library offers several PicoBlaze devices and code routines to extend a common PicoBlaze environment to a little System on a Chip (SoC or SoFPGA).

15.6K lines of code

0 current contributors

almost 10 years since last commit

1 users on Open Hub

Inactive
5.0
 
0 Reviews
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Mostly written in VHDL
Licenses: apache_2
Tags 8-bit altera kcpsm library opbasm picoblaze synthesis system-on-chip vhdl xilinx

vhdl-extras

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  Analyzed about 9 hours ago

This library provides some "extra" bits of code that are not found in the standard VHDL libraries. With VHDL-extras you can create designs that will resize to varying data widths, compute with time, frequency, and clock cycles, include error correction, and many more commonly encountered issues in ... [More] digital logic design. These packages can be used for logic simulations and, in most cases, can be synthesized to hardware with an FPGA or ASIC target. All of the packages are designed to work with VHDL-93. Alternate packages supporting newer VHDL standards are provided where new language features provide enhanced functionality or where forward compatibility is broken. The core code should work in most VHDL-93 compliant tools. [Less]

16K lines of code

0 current contributors

over 2 years since last commit

0 users on Open Hub

Inactive
4.0
   
0 Reviews
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Mostly written in VHDL
Licenses: mit
Tags asic fpga library open-source simulation synthesis vhdl