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OSVVM

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  Analyzed 1 day ago

Open Source VHDL Verification Methodology (OSVVM) is an intelligent testbench methodology that allows mixing of “Intelligent Coverage” (coverage driven randomization) with directed, algorithmic, file based, and constrained random test approaches. The methodology can be adopted in part or in whole as ... [More] needed. With OSVVM you can add advanced verification methodologies to your current testbench without having to learn a new language or throw out your existing testbench or testbench models. [Less]

109K lines of code

1 current contributors

about 1 month since last commit

3 users on Open Hub

Moderate Activity
5.0
 
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pyBAR

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  Analyzed 1 day ago

Bonn ATLAS Readout in Python and C++

32K lines of code

2 current contributors

over 5 years since last commit

0 users on Open Hub

Inactive
0.0
 
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Licenses: BSD-3-Clause, lgpl-v3

vhdl-extras

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  Analyzed about 10 hours ago

This library provides some "extra" bits of code that are not found in the standard VHDL libraries. With VHDL-extras you can create designs that will resize to varying data widths, compute with time, frequency, and clock cycles, include error correction, and many more commonly encountered issues in ... [More] digital logic design. These packages can be used for logic simulations and, in most cases, can be synthesized to hardware with an FPGA or ASIC target. All of the packages are designed to work with VHDL-93. Alternate packages supporting newer VHDL standards are provided where new language features provide enhanced functionality or where forward compatibility is broken. The core code should work in most VHDL-93 compliant tools. [Less]

16K lines of code

0 current contributors

10 months since last commit

0 users on Open Hub

Very Low Activity
4.0
   
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