Project Summary
This library provides some "extra" bits of code that are not found in the standard VHDL libraries. With VHDL-extras you can create designs that will resize to varying data widths, compute with time, frequency, and clock cycles, include error correction, and many more commonly encountered issues in digital logic design. These packages can be used for logic simulations and, in most cases, can be synthesized to hardware with an FPGA or ASIC target.
All of the packages are designed to work with VHDL-93. Alternate packages supporting newer VHDL standards are provided where new language features provide enhanced functionality or where forward compatibility is broken. The core code should work in most VHDL-93 compliant tools.
In a Nutshell, vhdl-extras...
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took an estimated 4 years of effort (COCOMO model)
starting with its first commit in November, 2010
ending with its most recent commit over 1 year ago
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MIT License
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These details are provided for information only. No information here is legal advice and should not be used as such.
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