Project Summary
The VVC Framework is a VHDL Verification Component system that allows multiple interfaces on a DUT to be stimulated/handled simultaneously in a very structured manner, and controlled by a very simple to understand software like a test sequencer. VVC Framework is unique as an open source VHDL approach to building a structured testbench architecture using Verification components and a simple protocol to access these. As an example a simple command like uart_expect(UART_VVCT, my_data), or axilite_write(AXILITE_VVCT, my_addr, my_data, my_message) will automatically tell the respective VVC (for UART or AXI-Lite) to execute the uart_receive() or axilite_write() BFM respectively.
In a Nutshell, UVVM...
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has a well established, mature codebase
maintained by a average size development team
with decreasing Y-O-Y commits -
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took an estimated 47 years of effort (COCOMO model)
starting with its first commit in January, 2016
ending with its most recent commit about 1 month ago
Quick Reference
MIT License
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These details are provided for information only. No information here is legal advice and should not be used as such.
Project Security
Vulnerabilities per Version ( last 10 releases )
There are no reported vulnerabilities
Project Vulnerability Report
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30 Day SummaryNov 3 2024 — Dec 3 2024
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12 Month SummaryDec 3 2023 — Dec 3 2024
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