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FPGALink
Analyzed 17 minutes ago
The aim of the FPGALink project is to provide a hardware abstraction layer for hardware involving an FPGA connected to a computer over USB, to abstract core functionality like FPGA-programming and subsequent host-FPGA communication. It doesn't matter whether the hardware uses an AVR, an FX2LP or an
Licenses:
GNU_Gener..., gpl3_or_l..., lgpv3_or_...
ZX Spectrum Next - Digilent Nexys A7-100T Port
Z
Analyzed about 20 hours ago
Port of the ZX Spectrum Next core to the Digilent Nexys A7-100T board.
Verilog Perl
V
Analyzed 12 months ago
The Verilog-Perl distribution provides Perl preprocessing, parsing and utilities for the Verilog Language. It is also available from CPAN under the Verilog:: namespace.
Licenses:
No declared licenses
Icarus SIMBUS
Analyzed 1 day ago
SIMBUS is a simulation tool for SoC and system level simulation of multiple devices connected by bus nodes. Client simulation models may be written in Verilog and C/C++.
Async SDM Router for On-Chip Networks
A
No analysis available
This project provide a reconfigurable asynchronous SDM router which can be configured
into a basic wormhole router or an SDM router with multiple virtual circuits in every
direction.
Features:
* 5-port router for mesh network (0 south, 1 west, 2 north, 3 east, 4 local)
* The dimension order
Mostly written in language not available
Licenses:
lgpl
Asynchronous-Verilog-Synthesiser
A
Analyzed about 18 hours ago
Synthesise Verilog and Asynchronous Verilog to netlists.
oldland-cpu
O
Analyzed about 23 hours ago
Oldland CPU - a 32-bit RISC FPGA CPU including RTL + tools
zamiacad
Z
Analyzed 1 day ago
zamiaCAD is a modular and extensible platform for HW design, analysis, and research. It translates a HW description (VHDL or Verilog) into a language independent IG structure. Applications like a simulator and an eclipse GUI build on top of the IG.
Licenses:
No declared licenses