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FPGALink

  Analyzed 17 minutes ago

The aim of the FPGALink project is to provide a hardware abstraction layer for hardware involving an FPGA connected to a computer over USB, to abstract core functionality like FPGA-programming and subsequent host-FPGA communication. It doesn't matter whether the hardware uses an AVR, an FX2LP or an ... [More] ARM-based micro for its USB interface. It doesn't matter whether the FPGA is from Xilinx or Altera or Lattice or whomever. It doesn't matter whether the interface between them is a fast 43MiB/s parallel synchronous interface, a much slower EPP interface or some sort of USART connection. The cross-platform, cross-language host-side API is the same, and the FPGA-side (VHDL or Verilog) FIFO interface is the same, so you can easily port your design to a new FPGA devkit or to your own custom PCB. [Less]

32.8K lines of code

0 current contributors

over 7 years since last commit

1 users on Open Hub

Inactive
0.0
 
I Use This
Licenses: GNU_Gener..., gpl3_or_l..., lgpv3_or_...

ZX Spectrum Next - Digilent Nexys A7-100T Port

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  Analyzed about 20 hours ago

Port of the ZX Spectrum Next core to the Digilent Nexys A7-100T board.

4.93M lines of code

0 current contributors

over 3 years since last commit

0 users on Open Hub

Inactive
0.0
 
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Verilog Perl

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  Analyzed 12 months ago

The Verilog-Perl distribution provides Perl preprocessing, parsing and utilities for the Verilog Language. It is also available from CPAN under the Verilog:: namespace.

17.7K lines of code

1 current contributors

almost 2 years since last commit

0 users on Open Hub

Activity Not Available
0.0
 
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Licenses: No declared licenses

Icarus SIMBUS

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  Analyzed 1 day ago

SIMBUS is a simulation tool for SoC and system level simulation of multiple devices connected by bus nodes. Client simulation models may be written in Verilog and C/C++.

15K lines of code

1 current contributors

about 6 years since last commit

0 users on Open Hub

Inactive
0.0
 
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Tags c cad eda verilog

Async SDM Router for On-Chip Networks

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  No analysis available

This project provide a reconfigurable asynchronous SDM router which can be configured into a basic wormhole router or an SDM router with multiple virtual circuits in every direction. Features: * 5-port router for mesh network (0 south, 1 west, 2 north, 3 east, 4 local) * The dimension order ... [More] routing (XY routing) * Available flow control methods: wormhole, SDM, VC * Reconfigurable number of virtual circuits, buffer size, data width * Fully synthesizable router implementation * SystemC testbench provided [Less]

0 lines of code

0 current contributors

0 since last commit

0 users on Open Hub

Activity Not Available
0.0
 
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Mostly written in language not available
Licenses: lgpl

Asynchronous-Verilog-Synthesiser

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  Analyzed about 18 hours ago

Synthesise Verilog and Asynchronous Verilog to netlists.

37.1K lines of code

0 current contributors

about 11 years since last commit

0 users on Open Hub

Inactive
0.0
 
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Tags eda verilog

someAVR

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  Analyzed about 23 hours ago

Small part of AVR CPU Core

458 lines of code

0 current contributors

almost 13 years since last commit

0 users on Open Hub

Inactive
0.0
 
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Tags avr verilog

oldland-cpu

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  Analyzed about 23 hours ago

Oldland CPU - a 32-bit RISC FPGA CPU including RTL + tools

29.2K lines of code

0 current contributors

over 10 years since last commit

0 users on Open Hub

Inactive
0.0
 
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zamiacad

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  Analyzed 1 day ago

zamiaCAD is a modular and extensible platform for HW design, analysis, and research. It translates a HW description (VHDL or Verilog) into a language independent IG structure. Applications like a simulator and an eclipse GUI build on top of the IG.

1.3M lines of code

0 current contributors

over 8 years since last commit

0 users on Open Hub

Inactive
0.0
 
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Licenses: No declared licenses
Tags verilog vhdl

verible

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  Analyzed 34 minutes ago

Verible provides a SystemVerilog parser, style-linter, and formatter.

170K lines of code

0 current contributors

2 months since last commit

0 users on Open Hub

Low Activity
0.0
 
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