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Analyzed 11 months ago. based on code collected about 3 years ago.

Commit Message	Contributor	Files Modified	Lines Added	Lines Removed	Code Location	Date
Mar 09, 2021 — Mar 09, 2022 Showing page 1,687 of 1,750 Search / Filter on:
Added yosys-svgviewer to build system and renamed filterlib to yosys-filterlib	Clifford Wolf	More...				about 12 years ago
Imported svgviewer from qt4.8	Clifford Wolf	More...				about 12 years ago
More GVariant conversions	Bert Vermeulen	More...				about 12 years ago
Weird, I thought I fixed this bug earlier but it magically reappeared again.	Jason Luu	More...				about 12 years ago
VPR spurts outs way too many warnings so I increased the warning limit so that we don't get a fatal error for reaching that limit.	Jason Luu	More...				about 12 years ago
Simple auto forced pack code. If an unused primitive drives existing logic inside a cluster via a forced connection (interconnect that has no flexibility), then only the atom that can potentially get absorbed into that is considered. All other atoms are rejected from using that position.	Jason Luu	More...				about 12 years ago
Remove LUT from carry chain, have the tool auto-pack the LUT in	Jason Luu	More...				about 12 years ago
Create nice errors when calling RTLIL::Module::derive() of base class	Clifford Wolf	More...				about 12 years ago
Collect parameters in hierarchy -generate (and do nothing with them)	Clifford Wolf	More...				about 12 years ago
Tiny bugfix in simlib.v	Clifford Wolf	More...				about 12 years ago
Improvements and bugfixes for generate blocks with local signals	Clifford Wolf	More...				about 12 years ago
Fixed handling of unconditional generate blocks	Clifford Wolf	More...				about 12 years ago
Adjust to GVariant-based sr_config_* functions	Bert Vermeulen	More...				about 12 years ago
Added nosync attribute and some async reset related fixes	Clifford Wolf	More...				about 12 years ago
Improved verbose output of subcircuit	Clifford Wolf	More...				about 12 years ago
Improved method for finding fsm_expand candidates	Clifford Wolf	More...				about 12 years ago
Added hierarchy -generate command for generating skeletton modules	Clifford Wolf	More...				about 12 years ago
Changed fsm_expand to merge multiplexers more aggressively	Clifford Wolf	More...				about 12 years ago
Renamed hansimem.v test case to mem_arst.v	Clifford Wolf	More...				about 12 years ago
Fixed handling of show -viewer	Clifford Wolf	More...				about 12 years ago
Fixed handling of internal signals in show command	Clifford Wolf	More...				about 12 years ago
Improved show -colors color assignments	Clifford Wolf	More...				about 12 years ago
Added show -strech and renamed -widthlabels to -width	Clifford Wolf	More...				about 12 years ago
Added -widthlabels options to chow command	Clifford Wolf	More...				about 12 years ago
Added -notypes option to intersynth backend	Clifford Wolf	More...				about 12 years ago
Reorganized TODOs	Clifford Wolf	More...				about 12 years ago
Added mem2reg option to verilog frontend	Clifford Wolf	More...				about 12 years ago
Fixed stdcells.v for $adff with undef reset value	Clifford Wolf	More...				about 12 years ago
Another fix in mem2reg ast simplify logic	Clifford Wolf	More...				about 12 years ago
Added -colors option to show command	Clifford Wolf	More...				about 12 years ago

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