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Commits
: Listings
Analyzed
11 months
ago. based on code collected
about 3 years
ago.
Mar 09, 2021 — Mar 09, 2022
Showing page 1,684 of 1,750
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Contributor
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Code Location
Date
Upgrade to latest arch file
Jason Luu
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about 12 years ago
Updating regression tests
Jason Luu
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about 12 years ago
Updating regression tests
Jason Luu
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about 12 years ago
Updating regression tests
Jason Luu
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about 12 years ago
Going through regression tests
Jason Luu
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about 12 years ago
git-svn-id: https://vtr-verilog-to-routing.googlecode.com/svn/trunk@1868 8e3573b8-cf2c-4f14-ef6d-137439e28b8b
Jason Luu
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about 12 years ago
Upgrade to more accurate arch file slows down QoR
Jason Luu
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about 12 years ago
Upgrade to more accurate architecture file slows down this circuit
Jason Luu
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about 12 years ago
Since upgraded architecture file is slower (more realistic), the corresponding golden results need to be updated too.
Jason Luu
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about 12 years ago
Added a K4 N4 architecture
Jason Luu
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about 12 years ago
Removed unused models
Jason Luu
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about 12 years ago
sync arch names in QoR experiments
Jason Luu
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about 12 years ago
non heterogeneous frac lut architecture added
Jason Luu
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about 12 years ago
Update golden results to latest arch file
Jason Luu
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about 12 years ago
Update to latest arch files
Jason Luu
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about 12 years ago
git-svn-id: https://vtr-verilog-to-routing.googlecode.com/svn/trunk@1858 8e3573b8-cf2c-4f14-ef6d-137439e28b8b
Jason Luu
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about 12 years ago
Change regression tests to use latest architectures
Jason Luu
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about 12 years ago
update sample arch to reflect realistic numbers
Jason Luu
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about 12 years ago
Simplify list of architectures
Jason Luu
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about 12 years ago
Fixed buffer/wire capacitances for 22 and 130nm arch files.
Jeffrey Goeders
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about 12 years ago
GPL headers: Use correct project name.
Uwe Hermann
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about 12 years ago
README: Add "Copyright and license" section.
Uwe Hermann
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about 12 years ago
Open device before adding it to the session
Bert Vermeulen
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about 12 years ago
Add NSIS file for use with cross-compiled sigrok-cli.
Uwe Hermann
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about 12 years ago
Fixed two bugs in timing constraint calculation, added section on SDC files to user manual, added sample SDC files corresponding to manual
Michael Wainberg
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about 12 years ago
Fix minor bug in power code
Jeffrey Goeders
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about 12 years ago
git-svn-id: https://vtr-verilog-to-routing.googlecode.com/svn/trunk@1851 8e3573b8-cf2c-4f14-ef6d-137439e28b8b
Jason Luu
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about 12 years ago
Updated vpr manual and power manual.
Jeffrey Goeders
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about 12 years ago
Show driver name and optional conn string
Bert Vermeulen
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about 12 years ago
My pass through User Manual done
Jason Luu
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about 12 years ago
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