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Analyzed 11 months ago. based on code collected about 3 years ago.

Commit Message	Contributor	Files Modified	Lines Added	Lines Removed	Code Location	Date
Mar 09, 2021 — Mar 09, 2022 Showing page 1,688 of 1,750 Search / Filter on:
Added hansimem testcase (memory with async reset)	Clifford Wolf	More...				about 12 years ago
Improved mem2reg handling in ast simplifier	Clifford Wolf	More...				about 12 years ago
Fixed gcc build (intersynth backend)	Clifford Wolf	More...				about 12 years ago
Tiny fixes to verilog parser	Clifford Wolf	More...				about 12 years ago
Various improvements in intersynth backend	Clifford Wolf	More...				about 12 years ago
Added intersynth backend	Clifford Wolf	More...				about 12 years ago
Update power estimation methods and cleanup power output file.	Jeffrey Goeders	More...				about 12 years ago
Change power reg test to use new arch.	Jeffrey Goeders	More...				about 12 years ago
Arch file white space formatting	Jeffrey Goeders	More...				about 12 years ago
Add power #s to architecture file	Jeffrey Goeders	More...				about 12 years ago
Added help -write-tex-command-reference-manual option	Clifford Wolf	More...				about 12 years ago
Added eclipse CDT project files to .gitignore	Clifford Wolf	More...				about 12 years ago
Added -S option for simple synthesis to gate logic	Clifford Wolf	More...				about 12 years ago
Avoid verilog-2k in verilog backend	Clifford Wolf	More...				about 12 years ago
Disabled the per-default dumping of ILANG code	Clifford Wolf	More...				about 12 years ago
Added -nomap option to memory pass	Clifford Wolf	More...				about 12 years ago
update internal developer comments to more sensible developer comments	Jason Luu	More...				about 12 years ago
Fixed the number of bits. Disabled the threshold for extra bits.	Salihir Wang	More...				about 12 years ago
Use Stratix IV matched architecture file	Jason Luu	More...				about 12 years ago
Use dedicated fpu parse file	Jason Luu	More...				about 12 years ago
Update golden results with more optimized values	Jason Luu	More...				about 12 years ago
"adder size" in Odin II did not do what I thought it did. The functionality where a user adder that is smaller than X bits gets synthesized to soft logic whereas larger adders get synthesized to hard logic is actually spec'ed by the "threshold_size" parameter	Jason Luu	More...				about 12 years ago
Added more parse files	Jason Luu	More...				about 12 years ago
Changed version number for ABC to match VTR version that it works on	Jason Luu	More...				about 12 years ago
Fixed bug where libarchfpga does not always get recompiled	Jason Luu	More...				about 12 years ago
Changed version to VPR 7.0	Jason Luu	More...				about 12 years ago
Added missing carry chain links	Jason Luu	More...				about 12 years ago
fix time-based limit logic	Bert Vermeulen	More...				about 12 years ago
Merge branch 'hansiglaser-master'	Clifford Wolf	More...				about 12 years ago
added optimizations for single-bit $eq/$ne with constant input to opt_const	Clifford Wolf	More...				about 12 years ago

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