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Analyzed 11 months ago. based on code collected about 3 years ago.

Commit Message	Contributor	Files Modified	Lines Added	Lines Removed	Code Location	Date
Mar 09, 2021 — Mar 09, 2022 Showing page 1,691 of 1,750 Search / Filter on:
Added support for attribute matching in extract pass	Clifford Wolf	More...				about 12 years ago
Added portmapping support to subcircuit userCompareNodes() api	Clifford Wolf	More...				about 12 years ago
Cleanups and improvements in Makefile	Clifford Wolf	More...				about 12 years ago
UVM 1.1d from Accellera.com	Accellera	More...				about 12 years ago
Average the LUT delays	Jason Luu	More...				about 12 years ago
Keeping carry chain architectures consistent with non carry chain	Jason Luu	More...				about 12 years ago
Updated comments on where all the delays came from. Made logic block crossbar delays and 36x36 multiplier delays more accurate.	Vaughn Betz	More...				about 12 years ago
More robust coding	Jason Luu	More...				about 12 years ago
Add another power task	Jeffrey Goeders	More...				about 12 years ago
Update for UBC job server only	Jeffrey Goeders	More...				about 12 years ago
Add another power task	Jeffrey Goeders	More...				about 12 years ago
Cleanup intermediate files in run_vtr_flow Sparse crossbar architectures	Jeffrey Goeders	More...				about 12 years ago
Should increase max # iterations on crit path route to prevent rare cases where minW*1.3 requires more than 50 iterations to route.	Jason Luu	More...				about 12 years ago
Fixed parsing of select #x<num> operator	Clifford Wolf	More...				about 12 years ago
Improved error message on failed module load	Clifford Wolf	More...				about 12 years ago
Added support for loadable modules (aka plugins)	Clifford Wolf	More...				about 12 years ago
Reset Makefile default config setting (oops)	Clifford Wolf	More...				about 12 years ago
Fixed mine test case for subcircuit library	Clifford Wolf	More...				about 12 years ago
Fixed handling of constant values and port swapping in subcircuit library	Clifford Wolf	More...				about 12 years ago
bias packer to use lower number pins of LUTs	Jason Luu	More...				about 12 years ago
Correct up delays	Jason Luu	More...				about 12 years ago
Completed carry chain architecture modelling	Jason Luu	More...				about 12 years ago
Changed default value for extract -mine_cells_span	Clifford Wolf	More...				about 12 years ago
fixed architecture file	Jason Luu	More...				about 12 years ago
fix SR_DF_END flow	Bert Vermeulen	More...				about 12 years ago
Monolithic carry-chain architecture	Jason Luu	More...				about 12 years ago
Commented up flagship architecture	Jason Luu	More...				about 12 years ago
properly check for result after output module data()	Bert Vermeulen	More...				about 12 years ago
Completed draft of area and delay models for flagship architecture	Jason Luu	More...				about 12 years ago
Completed inputting of all delay values except for logic tile area	Jason Luu	More...				about 12 years ago

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