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Analyzed 12 months ago. based on code collected about 3 years ago.

Commit Message	Contributor	Files Modified	Lines Added	Lines Removed	Code Location	Date
Mar 09, 2021 — Mar 09, 2022 Showing page 1,685 of 1,750 Search / Filter on:
Update power tasks	Jeffrey Goeders	More...				about 12 years ago
Update for libsigrok datafeed callback API changes.	Martin Ling	More...				about 12 years ago
Small variable naming fix to avoid confusion.	Uwe Hermann	More...				about 12 years ago
configure.ac: Show $build, $host, and lib versions.	Uwe Hermann	More...				about 12 years ago
Fixed "show -format ..." command line parsing	Clifford Wolf	More...				about 12 years ago
Added "submod -name ..." support	Clifford Wolf	More...				about 12 years ago
Fixed a bug in AST frontend for cases with non-blocking assigned variables as case values	Clifford Wolf	More...				about 12 years ago
Fixed a bug in opt_const when optimizing 1-bit compares with constants	Clifford Wolf	More...				about 12 years ago
Update power tasks	Jeffrey Goeders	More...				about 12 years ago
Update power tasks	Jeffrey Goeders	More...				about 12 years ago
Update power tasks	Jeffrey Goeders	More...				about 12 years ago
git-svn-id: https://vtr-verilog-to-routing.googlecode.com/svn/trunk@1844 8e3573b8-cf2c-4f14-ef6d-137439e28b8b	Jason Luu	More...				about 12 years ago
Fix bug where memory power = energy, instead of energy/T	Jeffrey Goeders	More...				about 12 years ago
Began work on file formats	Jason Luu	More...				about 12 years ago
Edited up to placement options.	Jason Luu	More...				about 12 years ago
Removed deprecated option -num_regions	Jason Luu	More...				about 12 years ago
Put in new stuff about pack patterns, links between CLBs, and default Fc values. Need to now read over the manual.	Jason Luu	More...				about 12 years ago
update blif files for new Stratix IV aligned architecture for release	Jason Luu	More...				about 12 years ago
VTR release script generator update	Jason Luu	More...				about 12 years ago
Fixed an elusive corner case bug where if a single net connected to the same LUT multiple times (shouldn't ever happen with any good synthesis tool), VPR corrupts memory and crashes in weird ways.	Jason Luu	More...				about 12 years ago
SR_CONF_TIMEBASE and _VDIVS lists are now an array of tuples	Bert Vermeulen	More...				about 12 years ago
Merge branch 'master' of github.com:cliffordwolf/yosys	Clifford Wolf	More...				about 12 years ago
Fixed clock related parameter names for $memrd and $memwr in techlibs/simlib.v	Clifford Wolf	More...				about 12 years ago
Merge pull request #5 from hansiglaser/master	Clifford Wolf	More...				about 12 years ago
fsm_export: optionally use binary state encoding as state names instead of s0, s1, ...	Johann Glaser	More...				about 12 years ago
Merge pull request #4 from hansiglaser/master	Clifford Wolf	More...				about 12 years ago
fsm_export: specify KISS filename on command line	Johann Glaser	More...				about 12 years ago
Rename some power tasks. Update power architectures.	Jeffrey Goeders	More...				about 12 years ago
Rename some power tasks. Update power architectures.	Jeffrey Goeders	More...				about 12 years ago
Arch file: white space fix.	Jeffrey Goeders	More...				about 12 years ago

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