Managed Projects

GHDL

  Analyzed 1 day ago

GHDL is an open-source analyzer, compiler, simulator and (experimental) synthesizer for VHDL, a Hardware Description Language (HDL). GHDL provides full support for the 1987, 1993, 2002 versions of the IEEE 1076 VHDL standard, and partial for the 2008 revision. GHDL allows you to analyse and ... [More] elaborate sources for generating machine code from your design. [Less]

933K lines of code

18 current contributors

4 days since last commit

10 users on Open Hub

High Activity
4.66667
   
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[DUPLICATE] MINGW-packages

  Analyzed about 15 hours ago

Package scripts for MinGW-w64 targets to build under MSYS2.

4.11K lines of code

101 current contributors

9 days since last commit

2 users on Open Hub

Very Low Activity
5.0
 
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Tags packages

pyVHDLModel

  Analyzed about 22 hours ago

An abstract language model of VHDL written in Python.

7.52K lines of code

0 current contributors

about 1 month since last commit

2 users on Open Hub

Very Low Activity
5.0
 
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Electronic Design Automation Abstraction (EDA²)

  Analyzed about 2 hours ago

40.1K lines of code

0 current contributors

about 1 month since last commit

2 users on Open Hub

Very Low Activity
0.0
 
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Licenses: No declared licenses

pyTooling

  Analyzed 1 day ago

pyTooling is a collection of arbitrary useful classes, decorators, meta-classes and exceptions.

32K lines of code

0 current contributors

about 1 month since last commit

1 users on Open Hub

Moderate Activity
0.0
 
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Licenses: No declared licenses

Hardware Description Languages

  Analyzed about 17 hours ago

Resources for open source electronic design automation (EDA), focused on using Hardware Description Languages targeting FPGA (but not only).

18.7K lines of code

0 current contributors

4 days since last commit

1 users on Open Hub

Low Activity
0.0
 
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F4PGA

  Analyzed 1 day ago

611K lines of code

0 current contributors

6 months since last commit

1 users on Open Hub

Very Low Activity
0.0
 
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