Managed Projects

GHDL

  Analyzed about 5 hours ago

GHDL is an open-source analyzer, compiler, simulator and (experimental) synthesizer for VHDL, a Hardware Description Language (HDL). GHDL provides full support for the 1987, 1993, 2002 versions of the IEEE 1076 VHDL standard, and partial for the 2008 revision. GHDL allows you to analyse and ... [More] elaborate sources for generating machine code from your design. [Less]

877K lines of code

18 current contributors

1 day since last commit

9 users on Open Hub

High Activity
4.66667
   
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Electronic Design Automation Abstraction (EDA²)

  Analyzed about 21 hours ago

37.7K lines of code

0 current contributors

12 days since last commit

2 users on Open Hub

Very Low Activity
0.0
 
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Licenses: No declared licenses

[DUPLICATE] MINGW-packages

  Analyzed about 8 hours ago

Package scripts for MinGW-w64 targets to build under MSYS2.

3.82K lines of code

101 current contributors

1 day since last commit

2 users on Open Hub

Low Activity
5.0
 
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Tags packages

pyVHDLModel

  Analyzed about 14 hours ago

An abstract language model of VHDL written in Python.

6.61K lines of code

0 current contributors

2 months since last commit

2 users on Open Hub

Low Activity
5.0
 
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Hardware Description Languages

  Analyzed 1 day ago

Resources for open source electronic design automation (EDA), focused on using Hardware Description Languages targeting FPGA (but not only).

18.3K lines of code

0 current contributors

3 days since last commit

1 users on Open Hub

High Activity
0.0
 
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pyTooling

  Analyzed about 8 hours ago

pyTooling is a collection of arbitrary useful classes, decorators, meta-classes and exceptions.

21.8K lines of code

0 current contributors

1 day since last commit

1 users on Open Hub

High Activity
0.0
 
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Licenses: No declared licenses

F4PGA

  Analyzed about 20 hours ago

610K lines of code

0 current contributors

2 days since last commit

1 users on Open Hub

Moderate Activity
0.0
 
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