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Analyzed about 20 hours ago. based on code collected 1 day ago.

Project Summary

A Formal Verification Methodology to lower the adoption barriers for Formal Verification of ASIC and FPGA designs in the Space sector

Tags

asic formal-verification fpga psl verification vhdl

In a Nutshell, fvm...

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Project Security

Vulnerabilities per Version ( last 10 releases )

There are no reported vulnerabilities

Project Vulnerability Report

Security Confidence Index

Poor security track-record
Favorable security track-record

Vulnerability Exposure Index

Many reported vulnerabilities
Few reported vulnerabilities

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About Project Security

Languages

Python
86%
VHDL
11%
4 Other
3%

30 Day Summary

Sep 5 2026 — Oct 5 2026

12 Month Summary

Oct 5 2025 — Oct 5 2026
  • 418 Commits
    Down -141 (25%) from previous 12 months
  • 3 Contributors
    Down -1 (25%) from previous 12 months

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