Project Summary
Open Source VHDL Verification Methodology (OSVVM) is an intelligent testbench methodology that allows mixing of “Intelligent Coverage” (coverage driven randomization) with directed, algorithmic, file based, and constrained random test approaches. The methodology can be adopted in part or in whole as needed. With OSVVM you can add advanced verification methodologies to your current testbench without having to learn a new language or throw out your existing testbench or testbench models.
In a Nutshell, OSVVM...
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has a well established, mature codebase
maintained by a average size development team
with stable Y-O-Y commits -
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took an estimated 37 years of effort (COCOMO model)
starting with its first commit in December, 2015
ending with its most recent commit about 1 month ago
Apache License 2.0
Permitted
Commercial Use
Modify
Distribute
Place Warranty
Sub-License
Private Use
Use Patent Claims
Forbidden
Hold Liable
Use Trademarks
Required
Include Copyright
State Changes
Include License
Include Notice
These details are provided for information only. No information here is legal advice and should not be used as such.
Project Security
Vulnerabilities per Version ( last 10 releases )
There are no reported vulnerabilities
Project Vulnerability Report
Security Confidence Index
Vulnerability Exposure Index
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30 Day SummaryJun 13 2026 — Jul 13 2026
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12 Month SummaryJul 13 2025 — Jul 13 2026
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