wsong83

Manchester, UK

Managed Projects

vpreproc

V

Analyzed 1 day ago

A Preprocessor for Verilog HDL written in C++

4.04K lines of code

0 current contributors

about 12 years since last commit

1 users on Open Hub

Inactive

I Use This

Mostly written in C++

Licenses: gpl3_or_l...

cpptcl

C

Analyzed 1 day ago

C++/Tcl, a library that allows to easily integrate C++ and Tcl.

5.81K lines of code

0 current contributors

about 6 years since last commit

1 users on Open Hub

Inactive

I Use This

Mostly written in C++

Licenses: gpl3_or_l...

Async SDM Router for On-Chip Networks

A

No analysis available

This project provide a reconfigurable asynchronous SDM router which can be configured into a basic wormhole router or an SDM router with multiple virtual circuits in every direction. Features: * 5-port router for mesh network (0 south, 1 west, 2 north, 3 east, 4 local) * The dimension order ... [More]

0 lines of code

0 current contributors

0 since last commit

0 users on Open Hub

Activity Not Available

I Use This

Mostly written in language not available

Tags network noc verilog vlsi

Asynchronous-Verilog-Synthesiser

A

Analyzed 1 day ago

Synthesise Verilog and Asynchronous Verilog to netlists.

37.1K lines of code

0 current contributors

over 9 years since last commit

0 users on Open Hub

Inactive

I Use This

Mostly written in C++

Tags eda verilog

cppSaif

C

Analyzed about 13 hours ago

cpp parser for SAIF file

548 lines of code

0 current contributors

about 4 years since last commit

0 users on Open Hub

Inactive

I Use This

Mostly written in C++