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Commits : Listings

Analyzed 1 day ago. based on code collected 1 day ago.
Nov 16, 2024 — Nov 16, 2025
Commit Message Contributor Files Modified Lines Added Lines Removed Code Location Date
build: add make init-force for reliable checkout (#5200)
Xu, Zefan
More... 5 days ago
submodule(CoupledL2): bump CoupledL2 (#5190)
zhanglinjuan
More... 6 days ago
README: fix a typo (#5193)
Osama Abdelkader
More... 7 days ago
ci(nightly): use make init to checkout submodules (#5192)
Xu, Zefan
More... 9 days ago
feat(pma,pmp): parameterize PMPs and PMAs (#5177)
Zhaoyang You
More... 9 days ago
fix(TLB): gpaddr should be same to vaddr when onlyS2 (#5189)
Xu, Zefan
More... 9 days ago
perf(DCache, LDU): add perfEvent in L1 DCache (#5166)
Huijin Li
More... 10 days ago
fix(VsegmentUnit): fix latch of paddr when element is unalign (#5164)
lwd
More... 10 days ago
fix(L1TLB): ignore addr when when mbmc.BME = 1 & CMODE = 0 (#5182)
Xin Tian
More... 11 days ago
feat(StandAloneDevice): modify standalone device id from 1bit to 16bit (#5180)
zhaohong1988
More... 11 days ago
fix(icache): icache miss bubble
Muzi
More... 12 days ago
feat(pdb): add CI support and batch mode for XSPdb (#4994)
Song Fangyuan
More... 13 days ago
submodule(difftest): bump difftest (#5163)
Jiuyue Ma
More... 14 days ago
fix(PerfEvent): add events in backend
chengguanghui
More... 16 days ago
timing(PTW): remove SRAM blocks with shallow depth
good-circle
More... 17 days ago
timing(VSplit): optimize ICG timing
lihuijin
More... 17 days ago
fix(L1TLB): ignore addr when hfence.vvma or sfence.vma when v=1 (#5114)
Xu, Zefan
More... 18 days ago
feat(L2Top, XSTile): move IntBuffer for beu into L2Top for partition (#5110)
zhanglinjuan
More... 19 days ago
timing(ftq): replace 2-port sram with reg for better timing (#5142)
Muzi
More... 20 days ago
feat(bpu): Tage BaseTable and SCTable dual-port SRAM changed to single port with 2bank (#5094)
Yuandongliang
More... 25 days ago
feat(XSCore): PfCtrl add two-cycle delay from Backend to CoupledL2
lihuijin
More... 26 days ago
timing(LoadUnit): optimize RAW enqueue timing
lihuijin
More... 27 days ago
timing(DCache): delay PseudoError to MainPipe by one cycle
lihuijin
More... 29 days ago
feat(top): adapt difftest top interfaces (#5123)
Yinan Xu
More... about 1 month ago
timing(MemBlock): modify GatedValidRegNext to RegNext for some 1-bit signals
lihuijin
More... about 1 month ago
feat(XSCore): top level of XSCore should not have combinational logics
zhanglinjuan
More... about 1 month ago
feat(XSCore): pin of Backend should not be connected to 2 pins
zhanglinjuan
More... about 1 month ago
fix(Bitmap): fix bitmap check result wakeup `l0BitmapReg` logic (#5073)
Xin Tian
More... about 1 month ago
fix(Rob): redirect need waiting for all uop writeback
Anzooooo
More... about 2 months ago
fix(TLB): fix incorrect TLB level refill when has exception (#5087)
Haoyuan Feng
More... about 2 months ago