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Commits : Listings

Analyzed about 12 hours ago. based on code collected about 12 hours ago.
Nov 30, 2024 — Nov 30, 2025
Commit Message Contributor Files Modified Lines Added Lines Removed Code Location Date
Merge pull request #11 from sashimi-yzh/soft-mdu More... almost 7 years ago
fpga,board,zedboard: set coreclk to 60MHz More... almost 7 years ago
fpga,noop: add synchronizer to let corerstn across clock domain More... almost 7 years ago
noop: disable M extension More... almost 7 years ago
noop,CSR: add illegal instruction exception More... almost 7 years ago
Merge pull request #10 from sashimi-yzh/fpga-timer More... almost 7 years ago
fpga,board,zedboard: remove deleted signals to avoid warnings More... almost 7 years ago
device,AXI4Timer: maintain rvalid and bvalid until the channels are ready More... almost 7 years ago
device,AXI4Timer: temporarily fix the resp overflow issue More... almost 7 years ago
fpga,noop.tcl: move ILA to a clock region faster than 10MHz More... almost 7 years ago
fpga,board,common.tcl: remove deleted files More... almost 7 years ago
fpga: add timer and refactor devices More... almost 7 years ago
top: generate AXI4Timer with NOOPFPGA More... almost 7 years ago
device: add AXI4Timer More... almost 7 years ago
Merge pull request #8 from sashimi-yzh/sim-mmio More... almost 7 years ago
test,top,SimMMIO: add uartlite stat and ctrl registers and map them to zero reg More... almost 7 years ago
Merge pull request #7 from sashimi-yzh/axi More... almost 7 years ago
fpga,zedboard,rtl: set ID bits long enough to fix truncation bug More... almost 7 years ago
fpga,noop.tcl: use AXI to replace AHB bridges More... almost 7 years ago
Makefile: rename axi signals More... almost 7 years ago
top: expose axi ports More... almost 7 years ago
memory,AXI4: support the issue of aw and w not ready at the same time More... almost 7 years ago
memory: add delayer, but assertion fails about aw and w ready at the same time More... almost 7 years ago
memory: add axi4 More... almost 7 years ago
Merge pull request #6 from sashimi-yzh/fpga More... almost 7 years ago
fpga: add zedboard from labeled-riscv project More... almost 7 years ago
Merge pull request #5 from sashimi-yzh/readmemh More... almost 7 years ago
tools: add generator to generate readmemh files for loadMemoryFromFile More... almost 7 years ago
Merge pull request #4 from sashimi-yzh/ahb More... almost 7 years ago
memory: add AHBRAM and pass microbench More... almost 7 years ago