VeriWell Verilog Simulator

I Use This!

Inactive

Analyzed about 13 hours ago. based on code collected about 13 hours ago.

Project Summary

VeriWell is a full Verilog simulator. It supports nearly all of the IEEE1364-1995 standard, as well as PLI 1.0. Yes, VeriWell *is* the same simulator that was sold by Wellspring Solutions in the mid-1990 and was included with the Thomas and Moorby book

In a Nutshell, VeriWell Verilog Simulator...

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has had 31 commits made by 3 contributors
representing 76,674 lines of code
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is mostly written in C++
with a low number of source code comments
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has a well established, mature codebase
maintained by nobody
with stable Y-O-Y commits
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took an estimated 19 years of effort (COCOMO model)
starting with its first commit in September, 2005
ending with its most recent commit almost 10 years ago

Quick Reference

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Homepage

Code Locations:

:pserver:anonymous:@veriwell.cvs...

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This Project has No vulnerabilities Reported Against it

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