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Analyzed 1 day ago. based on code collected 1 day ago.

Commit Message	Contributor	Files Modified	Lines Added	Lines Removed	Code Location	Date
Apr 27, 2024 — Apr 27, 2025 Showing page 175 of 177 Search / Filter on:
Solution for integer casting to std_logic problem by Theo Kluter	Roberto Rigamonti	More...				almost 10 years ago
Merge pull request #24 from leadrien/master	REDS	More...				about 10 years ago
Remove hepia specific code	Adrien Lescourt	More...				about 10 years ago
Fixed errors in VHDL generation and added a new board	Roberto Rigamonti	More...				about 10 years ago
Removed commented out file	Roberto Rigamonti	More...				about 10 years ago
Update README.md	REDS	More...				about 10 years ago
Fixed severe VHDL generation bug	Roberto Rigamonti	More...				about 10 years ago
Merge branch 'master' of https://github.com/reds-heig/logisim-evolution	Roberto Rigamonti	More...				about 10 years ago
Updated portuguese translation	Roberto Rigamonti	More...				about 10 years ago
Update README.md	REDS	More...				about 10 years ago
Fixed severe bug in VHDL generation	Roberto Rigamonti	More...				about 10 years ago
Merge branch 'master' of https://github.com/reds-heig/logisim-evolution	Roberto Rigamonti	More...				about 10 years ago
Fixed error in TCL console	Roberto Rigamonti	More...				about 10 years ago
Update README.md	REDS	More...				about 10 years ago
Various bugfixes, added export in images from chronogram	Roberto Rigamonti	More...				about 10 years ago
Improved retro-compatibility with non-VHDL labels	Roberto Rigamonti	More...				over 10 years ago
Sorted member functions and reformatted code	Roberto Rigamonti	More...				over 10 years ago
Update README.md	REDS	More...				over 10 years ago
Added vector test -- from Cornell's university Logisim version	Roberto Rigamonti	More...				over 10 years ago
Added vector test -- from Cornell's university Logisim version	Roberto Rigamonti	More...				over 10 years ago
Minor changes from Cornell's Logisim version	Roberto Rigamonti	More...				over 10 years ago
Improvements to retro-compatibility of XML loading	Roberto Rigamonti	More...				over 10 years ago
Fixed the pattern replacement mechanism in retrocompatibility and added test	Roberto Rigamonti	More...				over 10 years ago
Update README.md	REDS	More...				over 10 years ago
Update README.md	REDS	More...				over 10 years ago
Added French partial translation and updated Portouguese one	Roberto Rigamonti	More...				over 10 years ago
Added designrulecheck on duplicated sheetnames (especially when adding logisim circuits as libraries). Fixed numeric_std problem in gates	Roberto Rigamonti	More...				over 10 years ago
Fixed nullPointerException when moving component	Roberto Rigamonti	More...				over 10 years ago
Fixed the behavior of the close button when circuit modified	Roberto Rigamonti	More...				over 10 years ago
Added test for invalid VHDL variables	Roberto Rigamonti	More...				over 10 years ago

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