Icarus Verilog

Settings | Report Duplicate

7

I Use This!

Moderate Activity

Commits : Listings

Analyzed 2 days ago. based on code collected 2 days ago.

Commit Message	Contributor	Files Modified	Lines Added	Lines Removed	Code Location	Date
Apr 22, 2024 — Apr 22, 2025 Showing page 338 of 339 Search / Filter on:
Core handles subsignal expressions.	steve	More...				almost 26 years ago
Make debug output file parameters.	steve	More...				about 26 years ago
Add to vvm proceedural memory references.	steve	More...				about 26 years ago
Add memories to the parse and elaboration phases.	steve	More...				about 26 years ago
Support sized decimal numbers, Fix operator precedence order.	steve	More...				about 26 years ago
Add some logical operators.	steve	More...				about 26 years ago
Support more operators, especially logical.	steve	More...				about 26 years ago
Add the AND and OR bitwise operators.	steve	More...				about 26 years ago
Prevent the duplicate allocation of ESignal objects.	steve	More...				about 26 years ago
Handle default case.	steve	More...				about 26 years ago
Add support for module parameters.	steve	More...				about 26 years ago
Mangle that handles device instance numbers.	steve	More...				about 26 years ago
Fix off-by-one placement of hex bytes in a number.	steve	More...				about 26 years ago
Elaborate gate ranges.	steve	More...				about 26 years ago
Do not generate code for signals, instead use the NetESignal node to generate gate-like signal devices.	steve	More...				about 26 years ago
Turn the NetESignal into a NetNode so that it can connect to the netlist. Implement the case statement. Convince t-vvm to output code for the case statement.	steve	More...				about 26 years ago
Parse and elaborate the Verilog CASE statement.	steve	More...				about 26 years ago
Carry some line info to the netlist, Dump line numbers for processes. Elaborate prints errors about port vector width mismatch Emit better handles null statements.	steve	More...				about 26 years ago
Ignore ivl.	steve	More...				about 26 years ago
Missing start methods.	steve	More...				about 26 years ago
Add the LineInfo class to carry the source file location of things. PGate, Statement and PProcess.	steve	More...				about 26 years ago
change the program name to ivl.	steve	More...				about 26 years ago
Support null target for generating no output.	steve	More...				about 26 years ago
Add startup after initialization.	steve	More...				over 26 years ago
Support the start() method.	steve	More...				over 26 years ago
Proberly print vectors in binary.	steve	More...				over 26 years ago
Function to calculate wire initial value.	steve	More...				over 26 years ago
Parse more UDP input edge descriptions.	steve	More...				over 26 years ago
VVM support for small sequential UDP objects.	steve	More...				over 26 years ago
Fully elaborate Sequential UDP behavior.	steve	More...				over 26 years ago

←
1
2
…
331
332
333
334
335
336
337
338
339
→