openhub.net
Black Duck Software, Inc.
Open Hub
Follow @
OH
Sign In
Join Now
Projects
People
Organizations
Tools
Blog
BDSA
Projects
People
Projects
Organizations
Forums
Icarus Verilog
Settings
|
Report Duplicate
7
I Use This!
×
Login Required
Log in to Open Hub
Remember Me
Moderate Activity
Commits
: Listings
Analyzed
about 23 hours
ago. based on code collected
about 23 hours
ago.
Nov 14, 2024 — Nov 14, 2025
Showing page 2 of 5
Search / Filter on:
Commit Message
Contributor
Files Modified
Lines Added
Lines Removed
Code Location
Date
Optimise Perl regression test scripts.
Martin Whitaker
More...
28 days ago
More cppcheck updates
Cary R
More...
about 1 month ago
Two compiler warning fixes.
Martin Whitaker
More...
about 1 month ago
Update exe and manual pages to report @(C) 2025
Cary R
More...
about 1 month ago
Some cppcheck cleanup
Cary R
More...
about 1 month ago
Fix compile warning
Cary R
More...
about 1 month ago
Fix some new compiler warnings seen when using GCC 15 and clang 21.
Martin Whitaker
More...
about 1 month ago
Post-snapshot cleanup
Martin Whitaker
More...
about 1 month ago
Creating snapshot s20251012
Martin Whitaker
More...
about 1 month ago
Add a define for CC which is used by the iverilog-vpi script
Cary R
More...
about 1 month ago
Update config.guess and config.sub to latest versions
Cary R
More...
about 1 month ago
Fix builds using both --enable-suffix and --enable-libvvp options.
Martin Whitaker
More...
about 1 month ago
Fix suffixed vvp build under Windows.
Martin Whitaker
More...
about 1 month ago
Add regression test for issue #1273.
Martin Whitaker
More...
about 1 month ago
vvp: demangle identifiers when parsing the input file (issue #1273).
Martin Whitaker
More...
about 1 month ago
Add regression tests for $fmonitor tasks.
Martin Whitaker
More...
about 1 month ago
Add support for $fmonitor tasks (issue #1280)
Martin Whitaker
More...
about 1 month ago
Merge pull request #1270 from wsnyder/pr1008_finish
Cary R.
More...
2 months ago
Update pr1008.v to $finish
Wilson Snyder
More...
2 months ago
Move details of non-standard behaviour from README to Documentation.
Martin Whitaker
More...
3 months ago
Move documentation of additional system tasks from quirks to extensions.
Martin Whitaker
More...
3 months ago
Copy portability notes from old Wiki to new documentation area.
Martin Whitaker
More...
3 months ago
Update README to reflect current state of Verilog/SystemVerilog support.
Martin Whitaker
More...
3 months ago
Minor cppcheck updates in vvp and switch vvp to use override for virtual functions
Cary R
More...
4 months ago
Cleanup cppcheck suppression file
Cary R
More...
4 months ago
Fix and cleanup tgt-vp based on cppcheck results
Cary R
More...
4 months ago
Improve error messages when bad code is passed to the parser
Cary R
More...
4 months ago
Error when trying to elaborate a field of a simple variable
Cary R
More...
4 months ago
Add better error messages for output port elaboration issues
Cary R
More...
4 months ago
Calling front() on an empty() list is undefined
Cary R
More...
4 months ago
←
1
2
3
4
5
→
This site uses cookies to give you the best possible experience. By using the site, you consent to our use of cookies. For more information, please see our
Privacy Policy
Agree