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I Use This!
Moderate Activity
Analyzed about 3 hours ago. based on code collected about 3 hours ago.

Project Summary

Coordinating gateware development among many international collaborators is becoming a very widespread problem. Guaranteeing gateware synthesis with Place and Route reproducibility and assuring traceability of binary files is paramount.

Hog tackles these issues by exploiting advanced git features and integrating itself with HDL IDEs: Xilinx Vivado, Xilinx ISE (planAhead), Intel Quartus, Microchip Libero and Lattice Diamond. The integration with these tools intends to reduce as much as possible useless overhead work for the developers.

Tags

continuous_integration fpga git github github-action gitlab gitlab-ci tcl version_control

Apache License 2.0
Permitted

Commercial Use

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Distribute

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Sub-License

Private Use

Use Patent Claims

Forbidden

Hold Liable

Use Trademarks

Required

Include Copyright

State Changes

Include License

Include Notice

These details are provided for information only. No information here is legal advice and should not be used as such.

Project Security

Vulnerabilities per Version ( last 10 releases )

Project Vulnerability Report

Security Confidence Index

Poor security track-record
Favorable security track-record

Vulnerability Exposure Index

Many reported vulnerabilities
Few reported vulnerabilities

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About Project Security

Languages

Tcl
79%
shell script
20%
2 Other
1%

30 Day Summary

Apr 30 2025 — May 30 2025

12 Month Summary

May 30 2024 — May 30 2025
  • 413 Commits
    Down -37 (8%) from previous 12 months
  • 9 Contributors
    Down -5 (35%) from previous 12 months