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High Activity
Analyzed about 11 hours ago. based on code collected 1 day ago.

Project Summary

Coordinating gateware development among many international collaborators is becoming a very widespread problem. Guaranteeing gateware synthesis with Place and Route reproducibility and assuring traceability of binary files is paramount.

Hog tackles these issues by exploiting advanced git features and integrating itself with HDL IDEs: Xilinx Vivado, Xilinx ISE (planAhead), Intel Quartus, Microchip Libero and Lattice Diamond. The integration with these tools intends to reduce as much as possible useless overhead work for the developers.

Tags

continuous_integration fpga git github github-action gitlab gitlab-ci tcl version_control

In a Nutshell, Hog HDL-on-Git...

Apache License 2.0
Permitted

Commercial Use

Modify

Distribute

Place Warranty

Sub-License

Private Use

Use Patent Claims

Forbidden

Hold Liable

Use Trademarks

Required

Include Copyright

State Changes

Include License

Include Notice

These details are provided for information only. No information here is legal advice and should not be used as such.

Project Security

Vulnerabilities per Version ( last 10 releases )

Project Vulnerability Report

Security Confidence Index

Poor security track-record
Favorable security track-record

Vulnerability Exposure Index

Many reported vulnerabilities
Few reported vulnerabilities

Did You Know...

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About Project Security

Languages

Tcl
75%
shell script
14%
Python
11%
2 Other
<1%

30 Day Summary

Jun 14 2026 — Jul 14 2026

12 Month Summary

Jul 14 2025 — Jul 14 2026
  • 533 Commits
    Up + 55 (11%) from previous 12 months
  • 9 Contributors
    Down 0 (0%) from previous 12 months