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Analyzed about 5 hours ago. based on code collected about 5 hours ago.

Commit Message	Contributor	Files Modified	Lines Added	Lines Removed	Code Location	Date
Nov 17, 2024 — Nov 17, 2025 Showing page 2 of 672 Search / Filter on:
arch-riscv: fix load reserved store conditional	Adrià Armejach	More...				over 2 years ago
misc: Adding GitHub workflow files	Melissa Jost	More...				over 2 years ago
scons: Fix grpc protobuf actions	Roger Chang	More...				over 2 years ago
stdlib: Add U74VecFU to U74CPU	Roger Chang	More...				over 2 years ago
arch-arm: Apply FEAT_IDST to missing ID registers	Giacomo Travaglini	More...				over 2 years ago
gpu-compute: Gfx version check for FS and SE mode	Matthew Poremba	More...				over 2 years ago
stdlib: Fix incorrect path and checks for DRAMsim3	Bobby R. Bruce	More...				over 2 years ago
base: Output link to common errors page	Melissa Jost	More...				over 2 years ago
arch-arm: Add an ArmAllRelease containing every defined extension	Giacomo Travaglini	More...				over 2 years ago
scons: Add os import to marshall	Jason Lowe-Power	More...				over 2 years ago
dev-amdgpu: Update SDMA checkpointing	Matthew Poremba	More...				over 2 years ago
tests,systemc: Fix nightly systemc test	Bobby R. Bruce	More...				over 2 years ago
stdlib, tests, configs: Introduce gem5 Vision to resources	Kunal Pai	More...				over 2 years ago
scons: fix build failed caused by Non-ASCII directory path	Luming Wang	More...				over 2 years ago
stdlib: Edit RISCVMatched Configuration	KUNAL PAI	More...				over 2 years ago
arch-x86: Fix CPUID function 0	Matthew Poremba	More...				over 2 years ago
arch-arm: Extend auxiliary vector with AT_HWCAP2 entry	Giacomo Travaglini	More...				over 2 years ago
arch-arm: Enable FEAT_PAuth in SE mode	Giacomo Travaglini	More...				over 2 years ago
arch-arm: Define remaining fields of the arm64 AT_HWCAP entry	Giacomo Travaglini	More...				over 2 years ago
dev-amdgpu: Fix nbio psp ring assert	Matthew Poremba	More...				over 2 years ago
arch-arm: Fix printing of VecElemClass registers	Giacomo Travaglini	More...				over 2 years ago
arch-riscv: Fix WFI for O3 CPU	Bobby R. Bruce	More...				over 2 years ago
arch-arm: Fix position of AA64ISAR0.AES bitfield	Giacomo Travaglini	More...				over 2 years ago
sim,python: add activate option and method	Yan Lee	More...				over 2 years ago
base: add Activate to enable log of particular targets	Yan Lee	More...				over 2 years ago
arch-riscv: Merge rv32 and rv64 version of xperm4 and xperm8	Roger Chang	More...				over 2 years ago
arch-riscv: Simplify the rev8 and brev8 instructions	Roger Chang	More...				over 2 years ago
arch-riscv: Add BS format isa	Roger Chang	More...				over 2 years ago
arch-gcn3,arch-vega: Fix ds_read2st64_b32	Matthew Poremba	More...				over 2 years ago
arch-riscv: Simplify amd merge RV32/RV64 the RVM instructions	Roger Chang	More...				over 2 years ago

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