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Commits : Listings

Analyzed about 20 hours ago. based on code collected about 20 hours ago.
Nov 05, 2024 — Nov 05, 2025
Commit Message Contributor Files Modified Lines Added Lines Removed Code Location Date
Fix #352 GenCustomInterrupt demo More... over 2 years ago
Update DBusSimplePlugin.scala More... over 2 years ago
Merge pull request #350 from AdDraw/master More... over 2 years ago
Update DBusSimplePlugin.scala More... over 2 years ago
Add halfPipe function to DBusSimpleBus More... over 2 years ago
Update SpinalHDL More... over 2 years ago
fix fpu underflow rounding (#343) More... over 2 years ago
Add a few privSpec tests More... over 2 years ago
DBusCachedPlugin now provide writesPending signal More... over 2 years ago
d$ toBmb increase aggregation timer More... over 2 years ago
CsrPlugin now implement dummy HPM More... over 2 years ago
fix #328 medeleg EBREAK added More... over 2 years ago
Merge pull request #327 from andreasWallner/remove_sbt_assembly More... over 2 years ago
Remove sbt-assembly dependency More... over 2 years ago
sync More... over 2 years ago
Merge remote-tracking branch 'origin/dev' More... over 2 years ago
Revert CfuPlugin More... over 2 years ago
implement dummy pmp as 1.10 spec says More... over 2 years ago
CsrPlugin implement dummy pmp if no pmp is there More... over 2 years ago
Ensure that fence.i wait d$ inflight write and reschedule the next instruction More... over 2 years ago
CsrPluginConfig more var More... over 2 years ago
SpinalHDL 1.8.1 / Merge branch 'dev' More... over 2 years ago
sync More... over 2 years ago
cleanup IBusDBusCachedTightlyCoupledRam More... over 2 years ago
VexRiscvBmbGenrator now use relaxedReset More... over 2 years ago
ClockDomainResetGeneratorIf introduction More... over 2 years ago
privSpec now check FPU dirty flag More... over 2 years ago
VexRiscvSmpCluster fullCsr improvement More... over 2 years ago
Implement counteren (1.10+ spec) More... over 2 years ago
Cfu add enableInit option More... over 2 years ago