Tags : Browse Projects

Select a tag to browse associated projects and drill deeper into the tag cloud.

nvc

Compare

  Analyzed about 14 hours ago

VHDL compiler and simulator

264K lines of code

0 current contributors

3 days since last commit

1 users on Open Hub

High Activity
0.0
 
I Use This
Licenses: No declared licenses

Java Modeling Language (JML)

Compare

  Analyzed about 24 hours ago

The Java Modeling Language (JML) is a behavioral interface specification language that can be used to specify the behavior of Java modules (as in design by contract -- DBC). It has many tools to do assertion checking, unit testing, etc.

92K lines of code

0 current contributors

over 6 years since last commit

1 users on Open Hub

Inactive
5.0
 
I Use This
Licenses: No declared licenses

Sequence Chart Studio

Compare

  Analyzed about 3 hours ago

A user-friendly drawing and verification tool for Message Sequence Charts (MSC, HMSC) and UML Sequence Diagrams. Integrated with Microsoft Visio.

1.37M lines of code

0 current contributors

about 8 years since last commit

1 users on Open Hub

Inactive
0.0
 
I Use This

Workcraft

Compare

  Analyzed about 18 hours ago

Workcraft provides a flexible common framework for the development of Interpreted Graph Models, including visual editing, (co-)simulation, synthesis and formal verification. With Workcraft, the user can design a system using the most appropriate formalism (or even different formalisms for the ... [More] subsystems), while still utilising the power of Petri net analysis techniques. The applications of the Workcraft are wide-ranging: from modelling concurrent algorithms and biological systems to designing asynchronous electronic circuits and investigating crimes. [Less]

290K lines of code

0 current contributors

11 days since last commit

1 users on Open Hub

Moderate Activity
5.0
 
I Use This

Whiley Compiler (WyC)

Compare

Claimed by Whiley Analyzed about 6 hours ago

Whiley is a programming language particularly suited to safety-critical systems. It is a hybrid object-oriented and functional programming language which employs extended static checking to eliminate errors at compile time, including divide-by-zero, array out-of-bounds and null dereference errors.

33.8K lines of code

1 current contributors

over 1 year since last commit

1 users on Open Hub

Very Low Activity
5.0
 
I Use This

cocotb

Compare

  Analyzed about 13 hours ago

Coroutine Co-simulation Test Bench

35.1K lines of code

39 current contributors

5 days since last commit

1 users on Open Hub

High Activity
3.0
   
I Use This

UVE-project

Compare

  Analyzed 2 days ago

The UVE project creates software that automatically generates verification testbenches (TB) written in SystemVerilog (SV) integrating the UVM methodology. UVE makes the development of verification environments rapid and simple. The generated TB performs random actions on the DUV. It provides a ... [More] graphical user interface, a code generator, compilation scripts and a library of verification IPs (VIP). One of the main innovations of UVE is a list of TODOs in the TB code to help finalizing the TB. This is especially useful for developers not familiar with SV and/or UVE, but also experienced developers profit from that task list. The graphical interface lets the user observe and navigate the structure of the generated testbench. Simulation is launched directly from the tool. [Less]

923K lines of code

1 current contributors

almost 6 years since last commit

1 users on Open Hub

Inactive
0.0
 
I Use This
Licenses: apache_2, AGPL3_or_...

PoC-Library

Compare

  Analyzed about 15 hours ago

IP Core Library - Published and maintained by the Chair for VLSI Design, Diagnostics and Architecture, Faculty of Computer Science, Technische Universität Dresden, Germany

52.9K lines of code

2 current contributors

about 4 years since last commit

1 users on Open Hub

Inactive
5.0
 
I Use This

skelp-verifier

Compare

  Analyzed 1 day ago

A Java library for validation which concentrates on providing a simple API with useful (and readable!) error messages, all while being highly configurable so that it's useful in your application code.

14.4K lines of code

0 current contributors

over 6 years since last commit

1 users on Open Hub

Inactive
0.0
 
I Use This

UVVM

Compare

  Analyzed about 13 hours ago

The VVC Framework is a VHDL Verification Component system that allows multiple interfaces on a DUT to be stimulated/handled simultaneously in a very structured manner, and controlled by a very simple to understand software like a test sequencer. VVC Framework is unique as an open source VHDL ... [More] approach to building a structured testbench architecture using Verification components and a simple protocol to access these. As an example a simple command like uart_expect(UART_VVCT, my_data), or axilite_write(AXILITE_VVCT, my_addr, my_data, my_message) will automatically tell the respective VVC (for UART or AXI-Lite) to execute the uart_receive() or axilite_write() BFM respectively. [Less]

117K lines of code

3 current contributors

21 days since last commit

1 users on Open Hub

Low Activity
4.0
   
I Use This