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PoC-Library

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  Analyzed about 15 hours ago

IP Core Library - Published and maintained by the Chair for VLSI Design, Diagnostics and Architecture, Faculty of Computer Science, Technische Universität Dresden, Germany

52.9K lines of code

2 current contributors

over 4 years since last commit

1 users on Open Hub

Inactive
5.0
 
0 Reviews
I Use This
Mostly written in VHDL
Licenses: apache_2
Tags aldec altera arithmetic cross-platform fifo fpga i2c ipcore lattice library mentorgraphics open-source 8 more...

opbasm

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  Analyzed about 19 hours ago

Opbasm is a free cross-platform assembler for the PicoBlaze-3 (PB3) and PicoBlaze-6 (PB6) microcontrollers provided by Xilinx. It will run readily on any platform with a Python interpreter. Opbasm provides a better performing solution to assembling PicoBlaze code without resorting to DOS or Windows ... [More] emulation to run the native KCPSM assemblers. [Less]

9.59K lines of code

2 current contributors

6 months since last commit

1 users on Open Hub

Very Low Activity
5.0
 
0 Reviews
I Use This
Mostly written in Python
Licenses: mit
Tags 8-bit assembler fpga kcpsm picoblaze processor soft-core verilog vhdl xilinx

SIMULinho

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  Analyzed about 7 hours ago

Simulador integrado iVerilog com interface QT, permite visualizar internamente e controlar a simulação do RISCuinho usando iVerilog

110 lines of code

0 current contributors

over 2 years since last commit

1 users on Open Hub

Inactive
0.0
 
0 Reviews
I Use This
Mostly written in C++
Licenses: No declared licenses
Tags fpga ieee1394 iverlog simulation synthesiser verilog

Solution-StopWatch

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  Analyzed about 1 hour ago

Professional VHDL Class Solution - StopWatch

3.64K lines of code

0 current contributors

almost 2 years since last commit

1 users on Open Hub

Very Low Activity
0.0
 
0 Reviews
I Use This
Mostly written in VHDL
Licenses: No declared licenses
Tags 7segment fpga solution stopwatch training vhdl vivado xilinx

mm - lm32 + SHA256

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  Analyzed about 22 hours ago

Miner Manager

27.7K lines of code

0 current contributors

over 9 years since last commit

0 users on Open Hub

Inactive
0.0
 
0 Reviews
I Use This
Mostly written in coq
Licenses: unlicense
Tags bitcoin fpga lm32 sha256

oldland-cpu

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  Analyzed about 12 hours ago

Oldland CPU - a 32-bit RISC FPGA CPU including RTL + tools

29.2K lines of code

0 current contributors

about 9 years since last commit

0 users on Open Hub

Inactive
0.0
 
0 Reviews
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Mostly written in coq
Licenses: GPL2
Tags fpga openhardware soft_core system_on_chip verilog

vhdl-extras

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  Analyzed about 11 hours ago

This library provides some "extra" bits of code that are not found in the standard VHDL libraries. With VHDL-extras you can create designs that will resize to varying data widths, compute with time, frequency, and clock cycles, include error correction, and many more commonly encountered issues in ... [More] digital logic design. These packages can be used for logic simulations and, in most cases, can be synthesized to hardware with an FPGA or ASIC target. All of the packages are designed to work with VHDL-93. Alternate packages supporting newer VHDL standards are provided where new language features provide enhanced functionality or where forward compatibility is broken. The core code should work in most VHDL-93 compliant tools. [Less]

16K lines of code

0 current contributors

11 months since last commit

0 users on Open Hub

Very Low Activity
4.0
   
0 Reviews
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Mostly written in VHDL
Licenses: mit
Tags asic fpga library open-source simulation synthesis vhdl

ZX Spectrum Next - Digilent Nexys A7-100T Port

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  Analyzed about 7 hours ago

Port of the ZX Spectrum Next core to the Digilent Nexys A7-100T board.

4.93M lines of code

0 current contributors

about 2 years since last commit

0 users on Open Hub

Inactive
0.0
 
0 Reviews
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Mostly written in VHDL
Licenses: gnu3
Tags Artix Digilent fpga Nexys Spectrum verilog vhdl Xilinx ZX

CTU CAN FD IP Core

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  Analyzed 4 months ago

Open-source CAN with Flexible Data-rate IP Core implemented in VHDL and associated SocketCAN Linux kernel driver. Project has been started at Czech Technical University in Prague. The core Integration with Zynq-7000 system: https://gitlab.fel.cvut.cz/canbus/zynq/zynq-can-sja1000-top ... [More] Integration with Intel EP4CGX15 based DB4CGX15 PCIe board: https://gitlab.fel.cvut.cz/canbus/pcie-ctu_can_fd [Less]

290K lines of code

0 current contributors

4 months since last commit

0 users on Open Hub

Activity Not Available
0.0
 
0 Reviews
I Use This
Mostly written in VHDL
Licenses: Commercial, GPL2, mit
Tags can canbus driver fpga linux vhdl zynq

RSD

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  Analyzed about 13 hours ago

RSD: RISC-V Out-of-Order Superscalar Processor

52.7K lines of code

0 current contributors

24 days since last commit

0 users on Open Hub

Low Activity
0.0
 
0 Reviews
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Mostly written in Ruby
Licenses: No declared licenses
Tags cpu fpga out_of_order risc_v