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Moderate Activity
Commits
: Listings
Analyzed
1 day
ago. based on code collected
1 day
ago.
Feb 16, 2025 — Feb 16, 2026
Showing page 1 of 157
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Merge some zcpu stuff with wire + add icons for new tools (#3525)
Astralcircle
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2 days ago
Merge pull request #3524 from llysdal/fpga-fixes
Lysdal
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5 days ago
Fixed error regarding FPGA infinite loop detection
Lysdal
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5 days ago
Merge pull request #3486 from Gabriel-V-Maia/add-curtime-gate
Anticept
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5 days ago
Merge pull request #3499 from llysdal/wire-fpga
Anticept
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5 days ago
Fix lua error (#3498)
Astralcircle
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5 days ago
Merge pull request #3500 from DerelictDrone/master
Anticept
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5 days ago
Don't need AddCSLuaFile on client
Astralcircle
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5 days ago
Add check if client didn't downloaded content for some reason
Astralcircle
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5 days ago
Recreate the folder every time it is deleted (fix from e2 editor)
Astralcircle
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5 days ago
Merge branch 'wire-fpga' of https://github.com/llysdal/wire into wire-fpga
Astralcircle
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5 days ago
Revert my commit
Astralcircle
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5 days ago
Merge branch 'wire-fpga' of https://github.com/llysdal/wire into wire-fpga
Astralcircle
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5 days ago
Update data version
Astralcircle
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5 days ago
Moved fpga help html to data_static
Lysdal
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5 days ago
Moved fpga help html
Lysdal
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5 days ago
Moved fpgachip default file to wire default data generator
Lysdal
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5 days ago
Remove more unnecessary comments
Lysdal
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6 days ago
Removed some unnecessary comments
Lysdal
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6 days ago
Fixed error regarding execution count sometimes not being set
Lysdal
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6 days ago
Removed personal contact and author for fpga
Lysdal
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6 days ago
Removed trailing whitespace
Lysdal
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6 days ago
Merged wire fpga autoload into wire load
Lysdal
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6 days ago
Convert indentation to using tabs
Lysdal
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6 days ago
Changed help HTML
Lysdal
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6 days ago
Fixed bug with visual nodes
Lysdal
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6 days ago
Removed unused variables
Lysdal
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6 days ago
Removed usages of ~=
Lysdal
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6 days ago
Fixed spelling mistake in Scr
Lysdal
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6 days ago
Removed unnecessary parentheses
Lysdal
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6 days ago
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