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verilog-utils

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Analyzed 1 day ago. based on code collected 1 day ago.

Project Summary

native Verilog pcap, littletoe, bcd, xml and hash modules, with Icarus testbenches

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In a Nutshell, verilog-utils...

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has had 62 commits made by 1 contributors
representing 9,297 lines of code
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is mostly written in coq
with an average number of source code comments
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has a young, but established codebase
maintained by nobody
with stable Y-O-Y commits
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took an estimated 3 years of effort (COCOMO model)
starting with its first commit in March, 2012
ending with its most recent commit about 10 years ago

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Code Locations:

https://github.com/shuckc/verilo...

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Code

Lines of Code

Activity

Commits per Month

Community

Contributors per Month

Languages

coq	93%
Python	5%
6 Other	2%

30 Day Summary

Dec 14 2024 — Jan 13 2025

0 Commits
0 Contributors

12 Month Summary

Jan 13 2024 — Jan 13 2025

0 Commits
0 Contributors

Most Recent Contributors

Chris Shucksmith

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