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Analyzed 4 months ago. based on code collected 4 months ago.

Commit Message	Contributor	Files Modified	Lines Added	Lines Removed	Code Location	Date
Oct 20, 2024 — Oct 20, 2025 Showing page 1 of 24 Search / Filter on:
Added support for Interface declarations updates in VHDL-2008. Generics can now include types, packages, procedures, and packages	aghoras	More...				almost 8 years ago
Added VHDL-2008 Test file	aghoras	More...				almost 8 years ago
Added test syntax for VHDL-2008	aghoras	More...				almost 8 years ago
Added support for VHDL-2008 context definition and context reference	aghoras	More...				almost 8 years ago
Added support for "force" and "release" VHDL-2008 keywords and syntax	aghoras	More...				about 9 years ago
Support Verilog-AMS keyword.	tadashi-k	More...				almost 10 years ago
Change version to 1.2.2.a	tadashi-k	More...				almost 10 years ago
Add syntax coloring of port, signal and constant.	tadashi-k	More...				almost 10 years ago
Applied patch to support some VHDL 2008 Features from Tickets #3, except upper and lower_case_letter.	tadashi-k	More...				almost 10 years ago
Applied patch to support some VHDL 2008 Features from Tickets #3, except upper and lower_case_letter.	tadashi-k	More...				almost 10 years ago
Change version to 1.2.1.c	tadashi-k	More...				over 10 years ago
Fix insert new line bug	tadashi-k	More...				over 10 years ago
Fix one character length selection occurrence	tadashi-k	More...				over 10 years ago
Change version to 1.2.1.b	tadashi-k	More...				over 10 years ago
Update outline database when selection is changed for occurrence marker	tadashi-k	More...				over 10 years ago
Fixed spelling	tadashi-k	More...				over 10 years ago
Fixed Auto Edit Strategy by Windows new line (\r\n)	tadashi-k	More...				over 10 years ago
Change version to 1.2.1.a for development build	tadashi-k	More...				over 10 years ago
Exactly matching for occurrence marker in Verilog.	tadashi-k	More...				over 10 years ago
Add AutoEditStrategy for Verilog multi-line comment	tadashi-k	More...				almost 11 years ago
Evaluate signal reference in Verilog condition operator	tadashi-k	More...				almost 11 years ago
Exclude Verilog signals from the full source code annotation hover	tadashi-k	More...				almost 11 years ago
Limit selection occurrence as whole word	tadashi-k	More...				almost 11 years ago
Fix unresolved variable problem start with "pr"	tadashi-k	More...				almost 11 years ago
Merge from Sjors Hettinga's repository	tadashi-k	More...				almost 11 years ago
Merge from Sjors Hettinga's repository	tadashi-k	More...				almost 11 years ago
update multi-line comment scanner in Verilog	tadashi-k	More...				almost 11 years ago
Removed backupfile	aghoras	More...				over 12 years ago
From Illian Dinev:	aghoras	More...				over 12 years ago
Debug Partition scanner of doxygen multi--line comment.	tadashi-k	More...				over 12 years ago

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