R

RISC-V BOOM

Settings | Report Duplicate

0

I Use This!

Very Low Activity

Commits : Listings

Analyzed 1 day ago. based on code collected 1 day ago.

Commit Message	Contributor	Files Modified	Lines Added	Lines Removed	Code Location	Date
Oct 25, 2024 — Oct 25, 2025 Showing page 79 of 79 Search / Filter on:
Clarified consts regarding ROB.	Christopher Celio	More...				over 11 years ago
ROB can now handle non-pow2 entries.	Christopher Celio	More...				over 11 years ago
Fixed bug with muldiv/mem fighting for write port	Christopher Celio	More...				over 11 years ago
Optimized nacks, decode; updated fence	Christopher Celio	More...				over 11 years ago
LSU now nacks if cache not ready.	Christopher Celio	More...				over 11 years ago
Fix JAL br-mask bug introduced in last commit.	Christopher Celio	More...				over 11 years ago
Moved is_br to decode table, shortened crit. path	Christopher Celio	More...				over 11 years ago
Moved busy-table read ports off critical path.	Christopher Celio	More...				over 11 years ago
Removed cache.nack from forwarding critical path.	Christopher Celio	More...				over 11 years ago
Moved exceptions off critical path; dcw improvements.	Christopher Celio	More...				over 11 years ago
Workaround introduced Chisel bug (def/val on Literal).	Christopher Celio	More...				over 11 years ago
Fixed critical path thru Decode.	Christopher Celio	More...				over 11 years ago
Delayed mispredict signal a cycle.	Christopher Celio	More...				over 11 years ago
Removed br logic off critical path in loadreqslot.	Christopher Celio	More...				over 11 years ago
Moved PC retrieval off critical path.	Christopher Celio	More...				over 11 years ago
Add uarch counters to BOOM.	Christopher Celio	More...				over 11 years ago
Fixed store-data forwarding bug.	Christopher Celio	More...				over 11 years ago
bug fixes - BTB/BHT jal bug; exception handling; fences; stores	Christopher Celio	More...				over 11 years ago
Added uarch counters; updated to new AUIPC	Christopher Celio	More...				over 11 years ago
Better handling of JAL in BP stage.	Christopher Celio	More...				over 11 years ago
Now passes CSR test. Found JAL prediction bug.	Christopher Celio	More...				over 11 years ago
Match new uncore hierarchy	Christopher Celio	More...				over 11 years ago
Bug fixing CSR privileged exceptions.	Christopher Celio	More...				over 11 years ago
Fixed BTB bug, CSR set/clr now work.	Christopher Celio	More...				over 11 years ago
Fixed jalr target calc bug	Christopher Celio	More...				over 11 years ago
Updated to new privileged RISC-V spec.	Christopher Celio	More...				almost 12 years ago
Compiles and runs.	Christopher Celio	More...				almost 12 years ago
now compiles with reference-chip	Christopher Celio	More...				almost 12 years ago
Initial commit of superscalar out-of-order processor	Christopher Celio	More...				almost 12 years ago

←
1
2
…
71
72
73
74
75
76
77
78
79
→