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Commits : Listings

Analyzed about 6 hours ago. based on code collected 1 day ago.
Aug 28, 2025 — Aug 28, 2026
Commit Message Contributor Files Modified Lines Added Lines Removed Code Location Date
Update examples to account for addressUnitBits property More... about 3 years ago
add registerFile as children of registerFile More... almost 4 years ago
Bugfix More... about 4 years ago
Prepare for release More... about 4 years ago
ipxact2v: Use import instead of include for typedefs More... about 4 years ago
Prepare for release More... over 4 years ago
Add IP-XACT to Verilog converter More... over 4 years ago
Fix README link in setup.py More... over 4 years ago
Support types in verilogwriter More... over 4 years ago
Clean up repo root More... over 4 years ago
replace <br> by <br/> More... over 4 years ago
Fix enumeratedValues printing More... over 4 years ago
gen_markdown.py: print names and descriptions More... over 4 years ago
Prepare for release More... over 4 years ago
Add verilogwriter.py More... over 4 years ago
Add missing "mask" attribute More... over 4 years ago
Add missing 'dim' attribute of 'register' element More... over 4 years ago
bugfixes More... over 4 years ago
Fix syntax error More... over 4 years ago
Fixed bug on enumerated type More... over 5 years ago
Update README.md More... over 5 years ago
update ipyxact More... almost 6 years ago
Prepare for release More... over 7 years ago
Avoid YAML warning by specifying safe loader More... over 7 years ago
Added support for parsing parameters of IP-XACT file. More... almost 8 years ago
Strip leading and trailing spaces from ints More... about 8 years ago
Return an int object to avoid errors with large numbers More... about 8 years ago
Add reset field on a register More... about 8 years ago
Add new API for IP-XACT 2014 built with generateDS More... over 8 years ago
Added address block type to the memory map More... over 8 years ago