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Commits : Listings

Analyzed about 2 hours ago. based on code collected about 19 hours ago.
Jan 02, 2024 — Jan 02, 2025
Commit Message Contributor Files Modified Lines Added Lines Removed Code Location Date
added "jammy" removed "precise"
Jamey Hicks
More... over 2 years ago
Update for python3
Jamey Hicks
More... about 3 years ago
add include files to 'scan_files' processing
John Ankcorn
More... about 4 years ago
added '.sv' for allowed extensions when looking up files to synthesize
John Ankcorn
More... over 4 years ago
v18.08.1
Jamey Hicks
More... over 6 years ago
Merge pull request #20 from acw1251/unmanaged-impl-constraint
Jamey Hicks
More... over 6 years ago
Added unmanaged impl constraints
acw1251
More... over 6 years ago
added comments to synth.tcl for writing out 'elaborated design' (all input verilog, before synthesis)
John Ankcorn
More... over 6 years ago
Merge branch 'master' into ubuntu
Jamey Hicks
More... over 6 years ago
packaged 18.05.1 for trusty, xenial, bionic
Jamey Hicks
More... over 6 years ago
version 18.05.1: supporting Ultrascale and Ultrascale plus
Jamey Hicks
More... over 6 years ago
added Zynq, Kinex, and Virtex Ultrascale families
Jamey Hicks
More... almost 8 years ago
Merge pull request #19 from csail-csg/master
Jamey Hicks
More... over 8 years ago
Added hierarchical flag for report_utilization
acw1251
More... over 8 years ago
Merge pull request #18 from cwchung90/master
Jamey Hicks
More... over 8 years ago
When a design includes DCI, FPGA_DONE is not set until DCI matching is done. (By default, match_cycle=2) If DCI matching fails, FPGA is not programmed properly.
Chanwoo Chung
More... over 8 years ago
comment out export simulation until we figure out how to specify simulation top
Jamey Hicks
More... over 8 years ago
export_simulation information when generating IP cores for Xilinx
Jamey Hicks
More... over 8 years ago
resynthesize module if the cores it used have changed
Jamey Hicks
More... almost 9 years ago
added a Vivado tcl script to report clock domains of output pins of a cell in a synthesized netlist
Jamey Hicks
More... almost 9 years ago
added makefile dependence on xdc files
Jamey Hicks
More... almost 9 years ago
releasing version 16.02.1
Jamey Hicks
More... almost 9 years ago
Merge tag 'v16.02.1' into ubuntu
Jamey Hicks
More... almost 9 years ago
version 16.02.1
Jamey Hicks
More... almost 9 years ago
check for non-zero length of $debug_nets
Jamey Hicks
More... about 9 years ago
clear MARK_DEBUG property if not using ILA to give vivado more flexibility to meet timing
Jamey Hicks
More... about 9 years ago
read_xdc after link_design, which seems to help with some constraints that were removed during place_design
Jamey Hicks
More... about 9 years ago
packaged 15.12.1
Jamey Hicks
More... about 9 years ago
Merge tag 'v15.12.1' into ubuntu
Jamey Hicks
More... about 9 years ago
v15.12.1
Jamey Hicks
More... about 9 years ago