dps8m

← Older revision Revision as of 17:14, 18 October 2025 Line 55: Line 55:       The current focus is now on working through the issues between the hardware simulation and MCS.   The current focus is now ... [More] on working through the issues between the hardware simulation and MCS. −   − == References ==   −   − The following table has links to various references (such as old manuals) that are actively in use for this proejct:   −   − {| class="wikitable"   − ! ID   − ! Description   − ! Link   − |-   − | AN85-01   − | SERIES 60 (LEVEL 68) MULTICS COMMUNICATION SYSTEM SYSTEM DESIGNERS' NOTEBOOK   − | [http://www.bitsavers.org/pdf/honeywell/large_systems/multics/AN85-01_commSysSDN_Oct79.pdf]   − |-   − | AN87-00A   − | SERIES 60 (LEVEL 68) MULTICS HARDWARE AND SOFTWARE FORMATS PROGRAM LOGIC MANUAL   − | [http://www.bitsavers.org/pdf/honeywell/large_systems/multics/AN87-00A_HwSwFmtsPLM_Mar80.pdf]   − |-   − | AY34-02B   − | 66/DPS, 68/DPS & DPS 8 DATANET 6641/6651/6661/6678 OPERATION   − | [http://www.bitsavers.org/pdf/honeywell/large_systems/datanet/AY34-02B_DATANET_Operation_Jun81.pdf]   − |-   − | CC75-01   − | MULTICS ADMINISTRATORS' MANUAL - COMMUNICATIONS   − | [http://www.bitsavers.org/pdf/honeywell/large_systems/multics/CC75-01B_adminManComms_Dec83.pdf]   − |-   − | CC92-01A   − | SERIES 60 (LEVEL 68) MULTICS PROGRAMMERS' MANUAL - COMMUNICATIONS INPUT/OUTPUT   − | [http://www.bitsavers.org/pdf/honeywell/large_systems/multics/CC92-01A_MPM_commIO_Jul82.pdf]   − |-   − | DC88-01   − | SERIES 60 (LEVEL 66) DATANET 6600 FRONT-END NETWORK PROCESSOR   − | [http://www.bitsavers.org/pdf/honeywell/large_systems/multics/swenson/dc88-01.790300.DC88-01.dn6600-fnp.88.pdf]   − |-   − | DD01   − | Datanet 355/6600 Macro Assembler Program   − | [http://www.bitsavers.org/pdf/honeywell/large_systems/multics/swenson/dd01-00.751200.mr-none.dn35-assembler.308.pdf]   − |-   − | FN01-03C   − | DATANET 66 SYSTEM AND INSTALLATION MANUAL   − | [http://www.bitsavers.org/pdf/honeywell/large_systems/datanet/FN01-03C_DATANET_66_System_Manual_May83.pdf]   − |}   [Less]

← Older revision Revision as of 17:14, 18 October 2025 Line 8: Line 8:       ''The DATANET provides the variety of interfaces required by the elements and protocols of a distributed system, as well as a ... [More] facility for dialog with the central system. By performing the tasks of message            management and message handling, the processor relieves the central system for other processing functions. The resources of the central system are called upon only when the message is submitted for information processing. However, some networking functions (e.g., a message switch) can be accommodated by the processor without any involvement of the host processor.''   ''The DATANET provides the variety of interfaces required by the elements and protocols of a distributed system, as well as a facility for dialog with the central system. By performing the tasks of message            management and message handling, the processor relieves the central system for other processing functions. The resources of the central system are called upon only when the message is submitted for information processing. However, some networking functions (e.g., a message switch) can be accommodated by the processor without any involvement of the host processor.''   +   +   + == References ==   +   + The following table has links to various references (such as old manuals) that are actively in use for this phase of the project:   +   + {| class="wikitable"   + ! ID   + ! Description   + ! Link   + |-   + | AN85-01   + | SERIES 60 (LEVEL 68) MULTICS COMMUNICATION SYSTEM SYSTEM DESIGNERS' NOTEBOOK   + | [http://www.bitsavers.org/pdf/honeywell/large_systems/multics/AN85-01_commSysSDN_Oct79.pdf]   + |-   + | AN87-00A   + | SERIES 60 (LEVEL 68) MULTICS HARDWARE AND SOFTWARE FORMATS PROGRAM LOGIC MANUAL   + | [http://www.bitsavers.org/pdf/honeywell/large_systems/multics/AN87-00A_HwSwFmtsPLM_Mar80.pdf]   + |-   + | AY34-02B   + | 66/DPS, 68/DPS & DPS 8 DATANET 6641/6651/6661/6678 OPERATION   + | [http://www.bitsavers.org/pdf/honeywell/large_systems/datanet/AY34-02B_DATANET_Operation_Jun81.pdf]   + |-   + | CC75-01   + | MULTICS ADMINISTRATORS' MANUAL - COMMUNICATIONS   + | [http://www.bitsavers.org/pdf/honeywell/large_systems/multics/CC75-01B_adminManComms_Dec83.pdf]   + |-   + | CC92-01A   + | SERIES 60 (LEVEL 68) MULTICS PROGRAMMERS' MANUAL - COMMUNICATIONS INPUT/OUTPUT   + | [http://www.bitsavers.org/pdf/honeywell/large_systems/multics/CC92-01A_MPM_commIO_Jul82.pdf]   + |-   + | DC88-01   + | SERIES 60 (LEVEL 66) DATANET 6600 FRONT-END NETWORK PROCESSOR   + | [http://www.bitsavers.org/pdf/honeywell/large_systems/multics/swenson/dc88-01.790300.DC88-01.dn6600-fnp.88.pdf]   + |-   + | DD01   + | Datanet 355/6600 Macro Assembler Program   + | [http://www.bitsavers.org/pdf/honeywell/large_systems/multics/swenson/dd01-00.751200.mr-none.dn35-assembler.308.pdf]   + |-   + | FN01-03C   + | DATANET 66 SYSTEM AND INSTALLATION MANUAL   + | [http://www.bitsavers.org/pdf/honeywell/large_systems/datanet/FN01-03C_DATANET_66_System_Manual_May83.pdf]   + |} [Less]

← Older revision Revision as of 17:35, 18 October 2025 (2 intermediate revisions by the same user not shown) Line 23: Line 23:   * Eric Swenson and Jeffrey Johnson – Provide invaluable emotional support and ... [More] encouragement, helping to sustain momentum and foster collaboration among the team.   * Eric Swenson and Jeffrey Johnson – Provide invaluable emotional support and encouragement, helping to sustain momentum and foster collaboration among the team.     − == Current State (as of 10/18/2025) == + == Project Phases ==     − It was determined the best route to implement this project was to start with the Datanet FNP. This is actually a stand-alone mini-computer (for the era) that + === Phase 1: Implement the Datanet FNP on an FPGA === − was designed around handling large numbers of terminals performing all terminal I/O and multiplexing via a single, direct interface link to the central system. + * This phase is attempting to implement the FNP on a DE-10 Lite FPGA Development Board.   + * Status: Currently in progress (see [[Datanet 6678 Front-End Network Processor]])     − It's been noted that it appears someone took the central system and chopped it in half to make the front end processor. Internally, it has a CPU and an IOM that + === Phase 2: Determine DPS8M Implementation Strategy === − interface to serial I/O cards of various types. The FNP can support asynchronous and synchronous communication links of several types. + * There has been some discussion around the best way to implement the rest of the system. There are two primary options: −   + *# Create a version of the DPS8M software simulator that runs on an ARM Core on an FPGA Development Board (such as the DE-10 Nano) and then start moving parts of it into the FPGA, probably starting with the SCU/RAM). − The goal of this phase has been to implement an FNP in an FPGA development board that communicates with the DPS8M software simulator just like the real FNP would + *#* This is the "inside out" approach. − have communicated with the original central system. + *#* The advantage here is that very high speed communications are possible with the internal ARM core connecting directly to the FPGA. −   + *#* The disadvantage here is that getting the DPS8 simulator working on the ARM core looks like it could be a difficult task. − This phase has been ongoing since 2021. The current state of the FNP is: + *# Start adding more peripheral device emulation using the DE-10 Lite to communicate with the software simulator (running on a Raspberry PI) in a manner similar to the FNP emulation. − * CPU fully implemented (18-bit words, 64KW of RAM, 98 instructions) + *#* This is the "outside in" approach. − ** AQ Register 36 bits (also addressable at separate 18-bit registers A and Q) + *#* The advantage of this approach is that simpler components are implemented first and grow in complexity as implementation proceeds providing a nice "ramp up" in FPGA skills and expertise. − ** Instruction Counter 15 bits + *#* The disadvantage is that an external, high-speed communications method is required between the Raspberry PI and the DE-10 Lite board. The initial thought is to create a 9-bit parallel bus between the PI and DE-10 for the simulated peripherals. This will certainly be fast enough for unit record devices and probably tape drives but when you add mass storage devices, will it be fast enough? − ** Index Register (3) 18 bits + − ** I/0 Channel Selector 6 bits + − ** Indicator Register 8 bits + − * Memory Paging Unit (allows access up to 256KW of RAM) + − * IOM initial framework implemented but no device emulation yet. + −   + − There was also a partial implementation of a software simulator for the FNP written in C. In order to better understand the implementation of the FNP before continuing + − on the FPGA implementation, it was decided to attempt to finish the software simulator first. A TCP/IP protocol was developed (by Charles Anthony) and implemented in a + − special branch of the DPS8M software simulator. The other end was implemented by Charles in the FNP C simulator and the simulator was enhanced to be able to bootload + − the Multics Communications System software, downloaded from the DPS8M simulator. + −   + − However, due to some significant limitations of the C implementation, and my (Dean S. Anderson) lack of understanding of it, I decided to do a full, multi-threaded + − implementation in a modern version of Java. That version is now mostly operational and can successfully bootload MCS and has a partial implementation of the HSLA + − (High Speed Line Adapter) that works via TCP/IP connections. Due to a lack of documentation of the HSLA/HMLC cards, however, there has been some issues in simulating + − the hardware so that MCS is happy with it. We are able to get some terminal I/O but there are significant issues that prevent actually logging in to Multics so far. + −   + − The current focus is now on working through the issues between the hardware simulation and MCS. + [Less]

← Older revision Revision as of 17:35, 18 October 2025 Line 8: Line 8:       ''The DATANET provides the variety of interfaces required by the elements and protocols of a distributed system, as well as a ... [More] facility for dialog with the central system. By performing the tasks of message            management and message handling, the processor relieves the central system for other processing functions. The resources of the central system are called upon only when the message is submitted for information processing. However, some networking functions (e.g., a message switch) can be accommodated by the processor without any involvement of the host processor.''   ''The DATANET provides the variety of interfaces required by the elements and protocols of a distributed system, as well as a facility for dialog with the central system. By performing the tasks of message            management and message handling, the processor relieves the central system for other processing functions. The resources of the central system are called upon only when the message is submitted for information processing. However, some networking functions (e.g., a message switch) can be accommodated by the processor without any involvement of the host processor.''   +   + == Current State (as of 10/18/2025) ==   +   + It was determined the best route to implement this project was to start with the Datanet FNP. This is actually a stand-alone mini-computer (for the era) that   + was designed around handling large numbers of terminals performing all terminal I/O and multiplexing via a single, direct interface link to the central system.   +   + It's been noted that it appears someone took the central system and chopped it in half to make the front end processor. Internally, it has a CPU and an IOM that   + interface to serial I/O cards of various types. The FNP can support asynchronous and synchronous communication links of several types.   +   + The goal of this phase has been to implement an FNP in an FPGA development board that communicates with the DPS8M software simulator just like the real FNP would   + have communicated with the original central system.   +   + This phase has been ongoing since 2021. The current state of the FNP is:   + * CPU fully implemented (18-bit words, 64KW of RAM, 98 instructions)   + ** AQ Register 36 bits (also addressable at separate 18-bit registers A and Q)   + ** Instruction Counter 15 bits   + ** Index Register (3) 18 bits   + ** I/0 Channel Selector 6 bits   + ** Indicator Register 8 bits   + * Memory Paging Unit (allows access up to 256KW of RAM)   + * IOM initial framework implemented but no device emulation yet.   +   + There was also a partial implementation of a software simulator for the FNP written in C. In order to better understand the implementation of the FNP before continuing   + on the FPGA implementation, it was decided to attempt to finish the software simulator first. A TCP/IP protocol was developed (by Charles Anthony) and implemented in a   + special branch of the DPS8M software simulator. The other end was implemented by Charles in the FNP C simulator and the simulator was enhanced to be able to bootload   + the Multics Communications System software, downloaded from the DPS8M simulator.   +   + However, due to some significant limitations of the C implementation, and my (Dean S. Anderson) lack of understanding of it, I decided to do a full, multi-threaded   + implementation in a modern version of Java. That version is now mostly operational and can successfully bootload MCS and has a partial implementation of the HSLA   + (High Speed Line Adapter) that works via TCP/IP connections. Due to a lack of documentation of the HSLA/HMLC cards, however, there has been some issues in simulating   + the hardware so that MCS is happy with it. We are able to get some terminal I/O but there are significant issues that prevent actually logging in to Multics so far.   +   + The current focus is now on working through the issues between the hardware simulation and MCS.         [Less]

‎Phase 2: Determine DPS8M Implementation Strategy ← Older revision Revision as of 17:40, 18 October 2025 (One intermediate revision by the same user not shown) Line 39: Line 39:   *#* The advantage of this ... [More] approach is that simpler components are implemented first and grow in complexity as implementation proceeds providing a nice "ramp up" in FPGA skills and expertise.   *#* The advantage of this approach is that simpler components are implemented first and grow in complexity as implementation proceeds providing a nice "ramp up" in FPGA skills and expertise.   *#* The disadvantage is that an external, high-speed communications method is required between the Raspberry PI and the DE-10 Lite board. The initial thought is to create a 9-bit parallel bus between the PI and DE-10 for the simulated peripherals. This will certainly be fast enough for unit record devices and probably tape drives but when you add mass storage devices, will it be fast enough?   *#* The disadvantage is that an external, high-speed communications method is required between the Raspberry PI and the DE-10 Lite board. The initial thought is to create a 9-bit parallel bus between the PI and DE-10 for the simulated peripherals. This will certainly be fast enough for unit record devices and probably tape drives but when you add mass storage devices, will it be fast enough?   + * Based on the above, this phase will consist of creating the 9-bit parallel bus between a Raspberry PI and the DE-10 Lite and adapting the FNP FPGA emulation to use this bus to communicate with the simulated IOM running on the Raspberry PI.   + ** Speed and throughput testing will be done to determine maximum data transfer rates and throughput using a set of "test harness" programs running on the PI and FPGA independent of the DPS8 simulation/emulation.   + * The follow-on phases will be determined once the above testing is complete. [Less]

‎News & Blog Entries ← Older revision Revision as of 17:47, 18 October 2025 (2 intermediate revisions by the same user not shown) Line 8: Line 8:       ''The DATANET provides the variety of interfaces ... [More] required by the elements and protocols of a distributed system, as well as a facility for dialog with the central system. By performing the tasks of message            management and message handling, the processor relieves the central system for other processing functions. The resources of the central system are called upon only when the message is submitted for information processing. However, some networking functions (e.g., a message switch) can be accommodated by the processor without any involvement of the host processor.''   ''The DATANET provides the variety of interfaces required by the elements and protocols of a distributed system, as well as a facility for dialog with the central system. By performing the tasks of message            management and message handling, the processor relieves the central system for other processing functions. The resources of the central system are called upon only when the message is submitted for information processing. However, some networking functions (e.g., a message switch) can be accommodated by the processor without any involvement of the host processor.''   +   + == News & Blog Entries ==   +   + * 2024/11/25: Blog entry ''Implementing the DN6678 CPU using an FPGA'' [https://dps8m.gitlab.io/blog/posts/20241125_DN6678/]   + * 2024/06/22: Blog entry ''New Project：Hardware (FPGA) DPS-8/M ∕ FNP Project'' [https://dps8m.gitlab.io/blog/posts/20240622_FPGA/]       == Current State (as of 10/18/2025) ==   == Current State (as of 10/18/2025) == Line 21: Line 26:       This phase has been ongoing since 2021. The current state of the FNP is:   This phase has been ongoing since 2021. The current state of the FNP is: − * CPU fully implemented (18-bit words, 64KW of RAM, 98 instructions) + * CPU fully implemented (18-bit words, 98 instructions)   ** AQ Register 36 bits (also addressable at separate 18-bit registers A and Q)   ** AQ Register 36 bits (also addressable at separate 18-bit registers A and Q)   ** Instruction Counter 15 bits   ** Instruction Counter 15 bits Line 27: Line 32:   ** I/0 Channel Selector 6 bits   ** I/0 Channel Selector 6 bits   ** Indicator Register 8 bits   ** Indicator Register 8 bits − * Memory Paging Unit (allows access up to 256KW of RAM) + * 64 KWord block RAM implemented   + * Memory Paging Unit implemented (allows access up to 256KW of RAM)   * IOM initial framework implemented but no device emulation yet.   * IOM initial framework implemented but no device emulation yet.     Line 41: Line 47:       The current focus is now on working through the issues between the hardware simulation and MCS.   The current focus is now on working through the issues between the hardware simulation and MCS. −         == References ==   == References == [Less]

Jeffrey H. Johnson (8659f1e6) at 04 Oct 07:22 Update font-rosy-multics to v1.0-20251004

Signed-off-by: Jeffrey H. Johnson [email protected]

Signed-off-by: Jeffrey H. Johnson [email protected]

Signed-off-by: Jeffrey H. Johnson [email protected]