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Analyzed 1 day ago. based on code collected 3 days ago.

Commit Message	Contributor	Files Modified	Lines Added	Lines Removed	Code Location	Date
Nov 09, 2024 — Nov 09, 2025 Showing page 4 of 535 Search / Filter on:
WAW hazards elimination (#2881)	Côme	More...				7 months ago
Fix 2943 (#2945)	AngelaGonzalezMarino	More...				7 months ago
Fix URLs to point to CV32A60X-specific files on RTDs. (#2938)	Mike Thompson	More...				7 months ago
docs: link to CV32A60X design documentation (#2931)	André Sintzoff	More...				7 months ago
Merge pull request #2619 from ThalesSiliconSecurity/dev/cvxif_cc	André Sintzoff	More...				7 months ago
CV32A60X ISA (#2922)	Mike Thompson	More...				7 months ago
CVXIF agent : add some randomization on issue packet to cover some condition in CC	Ayoub Jalali	More...				7 months ago
Merge pull request #2618 from ThalesSiliconSecurity/csr_hazard	André Sintzoff	More...				7 months ago
ISACOV : no need to cover RO csr for csr_hazard	Ayoub Jalali	More...				7 months ago
Fix https://github.com/openhwgroup/cva6/issues/2912 (#2916)	AngelaGonzalezMarino	More...				7 months ago
added license header	Tanuj Khandelwal	More...				7 months ago
INTG: update metadata	Cesar Fuguet	More...				7 months ago
INTG: add metadata to report	Cesar Fuguet	More...				7 months ago
INTG: add HPDcache report (april 25)	Cesar Fuguet	More...				7 months ago
Merge pull request #2617 from ThalesSiliconSecurity/dev/tune_cov	André Sintzoff	More...				7 months ago
ISACOV : fix separate covergroups to toggle bins as you need	Ayoub Jalali	More...				7 months ago
Merge pull request #2615 from ThalesSiliconSecurity/dev/tune_cov	André Sintzoff	More...				7 months ago
ISACOV : ignore RO csr for CSR write instruction	Ayoub Jalali	More...				7 months ago
ISACOV : update coverage model to tune coverage holes	Ayoub Jalali	More...				7 months ago
Merge pull request #2614 from ThalesSiliconSecurity/dev/psu	André Sintzoff	More...				7 months ago
spike disasm : don't optimaze jump instructions	Ayoub Jalali	More...				7 months ago
Merge pull request #2612 from ThalesSiliconSecurity/tune_fcov	Mike Thompson	More...				7 months ago
Merge pull request #2613 from ThalesSiliconSecurity/dev/disam	André Sintzoff	More...				7 months ago
updated script to be able to run regression	Tanuj Khandelwal	More...				7 months ago
Fix instruction tracer for superscalar mode (#2901)	Enrico Zelioli	More...				7 months ago
SPIKE DISAM : Don't optimize decode for addi	Ayoub Jalali	More...				7 months ago
[Spike][CV-X_IF] Do not use implicit x10 RD for CUS_ADD_RS3_RTYPE/CUS_CADD. (#2610)	Zbigniew Chamski	More...				7 months ago
ISACOV : no need to toggle all rd bits for bext & bexti	Ayoub Jalali	More...				7 months ago
Merge pull request #2609 from ThalesSiliconSecurity/fix_r7	André Sintzoff	More...				7 months ago
OBI assertion : be signal shouldn't be zero during address phase	Ayoub Jalali	More...				7 months ago

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