cgen

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Hi, I've defined OBJ_COMPLEX_RELC macro to enable complex relocations (from mep port) in my cpu port which seems to work well. But for gas to compile, the RELOC_IMPLIES_OVERFLOW attr must be defined in the cpu file (only in mep-core.cpu till now). ... [More] Shouldn't this attr be a general attribute rather than a target dependant attr, or are the complex relocs in cgen a very experimental feature we shouldn't use ? Thanks, Aurélien [Less]

A new automated cgen source snapshot is available ftp://sourceware.org/pub/cgen/snapshots/cgen-20110901.tar.bz2 1593410 bytes, cgen-snapshot-20110901 tag See also ftp://sourceware.org/pub/cgen/snapshots/

Generating sim files from a cpu file containing: (define-operand (name drli) (comment "destination register") (type h-gr) (index f-dli) (setter () (set (reg h-gr f-dli) newval)) ) works fine, however generating sid files gives: ... [More] Generating tomibf-semantics.cxx ... Canonicalizing instruction semantics ... Done canonicalization. Analyzing instruction set ... Performing sanity checks ... Done analysis. Computing sformat argument buffers ... ERROR: send: not an object VOID Backtrace: In ../../../../../../src/sid/src/sid/component/cgen-cpu/tomi/../../../../cgen/cos.scm: 255: 0 [error "send: not an object" VOID] In unknown file: ?: 1 [/object-error "send" VOID "not an object"] In ../../../../../../src/sid/src/sid/component/cgen-cpu/tomi/../../../../cgen/cos.scm: 245: 2 [apply #<procedure /object-error #> #] 244: 3* (if (not #) (apply /object-error #)) 1112: 4* [/object-check VOID "send"] In unknown file: ?: 5 [send VOID get-name] In ../../../../../../src/sid/src/sid/component/cgen-cp [Less]

Hi, I would like to define a pseudo instruction such as the mips "la" instruction to load a 32-bit  address using  2 16-bit move instructions with different operands to differentiate bfd howtos... How to handle this using cgen ? Thanks, Aurélien

Hi, I'm modifiying our existing sid port for our 16-bit MCU to add a branch instruction with a 22-bit pcrel offset. Here is the short description: (define-arch (name tam16) (default-alignment aligned) (insn-lsb0? #f) ...) (define-isa ... [More] (name tam16) (default-insn-bitsize 16) (base-insn-bitsize 16) (default-insn-word-bitsize 16)) (define-cpu (name tam16bf) (endian big) (word-bitsize 16) (insn-chunk-bitsize 0)) The new 22-bit pcrel branch instruction is 2-word long and the pcrel corresponding field is continuous. I tried to define it like this: (define-ifield (name f-pcrel22) (attrs PCREL-ADDR) (word-offset 0) (word-length 32) (start 10) (length 22) (mode INT) (encode (...)) (decode (...)))) The generated code for extraction this field in tam16bf_extract_sfmt_bsr22l tam16bf_extract_sfmt_bsr22l (tam16-decode.cxx file) is EXTRACT_MSB0_SINT (insn, 16, 10, 22), which I think is wrong (base insn are 16-bit long). [Less]

A new automated cgen source snapshot is available ftp://sources.redhat.com/pub/cgen/snapshots/cgen-20110801.tar.bz2 1586315 bytes, cgen-snapshot-20110801 tag See also ftp://sources.redhat.com/pub/cgen/snapshots/

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A new automated cgen source snapshot is available ftp://sources.redhat.com/pub/cgen/snapshots/cgen-20110701.tar.bz2 1585802 bytes, cgen-snapshot-20110701 tag See also ftp://sources.redhat.com/pub/cgen/snapshots/