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Moderate Activity

Commits : Listings

Analyzed about 8 hours ago. based on code collected about 11 hours ago.
Jun 18, 2024 — Jun 18, 2025
Commit Message Contributor Files Modified Lines Added Lines Removed Code Location Date
adiv5: Refactored the PIDR disassembly logic for the designer code into a new function More... 10 months ago
adiv5: Moved the PIDR macros into the internal header for ADIv6 reuse More... 10 months ago
adiv6: Implemented support for reading out resource bus component IDs and begun the process of building a ROM table handler More... 10 months ago
adiv5: Moved the CIDR definitions to the internal header so they can be reused by the ADIv6 implementation More... 10 months ago
adiv6: Adjusted the AP register encoding scheme to specify ADIv6 register addresses correctly More... 10 months ago
adiv5_swd: Overhaul the request builder with comments and cleaned up logic More... 10 months ago
adiv6: Began implementing AP read/write primitives More... 10 months ago
adiv6: Added some comments and fixed the masking on the resource base address More... 10 months ago
adiv6: Implemented handling for getting the base address for the debug resoures More... 10 months ago
adiv6: Moved the new ADIv6-specific handling into a new file as AP discovery under v6 is very different to v5 More... 10 months ago
adiv5: Implemented handling for discovering a DPv3+'s debug resource bus address width More... 10 months ago
common/stm32/traceswo: Fixed some of the entry conditions and decoder state reset conditions for the IRQ handler More... 10 months ago
deps: sync libopencm3 for usart_get_baudrate impls More... 10 months ago
platforms/blackpill-f4: Refresh README More... 10 months ago
swolisten: Add support for walking USB descriptors More... 10 months ago
target_flash: Prevent NULL dereference when detached from targets More... 10 months ago
meson: stlink, swlink, blackpill-f4: Default to Async TraceSWO More... 10 months ago
hydrabus: Update TraceSWO TIM macros More... 10 months ago
f4discovery: Update TraceSWO TIM macros More... 10 months ago
f072, f3: Update TraceSWO TIM macros More... 10 months ago
ctxlink: Update TraceSWO TIM macros More... 10 months ago
96b_carbon: Remove traceswo More... 10 months ago
github: Enabled parallel make workers with output-sync per build target More... 10 months ago
s32k3xx: Remove assert More... 10 months ago
command: added "Platform commands:" message before platform-specific commands in cmd_help More... 10 months ago
renesas_rz: RAM size auto-detection More... 10 months ago
stm32h5: Add SRAM alias for H503 at 0x20000000 More... 10 months ago
renesas_rz: set RAM size based on part_id More... 10 months ago
stm32h5: Replace DBGMCU base address for CPU access More... 10 months ago
stm32l4: Use the `priv` structure version of the `device` pointer, not the parameter in `stm32l4_configure_dbgmcu()` when configuring the DBGMCU More... 10 months ago