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Analyzed 11 months ago. based on code collected about 3 years ago.

Commit Message	Contributor	Files Modified	Lines Added	Lines Removed	Code Location	Date
Mar 09, 2021 — Mar 09, 2022 Showing page 1,703 of 1,750 Search / Filter on:
Added some additional TODO items	Clifford Wolf	More...				about 12 years ago
Fixed typo in README	Clifford Wolf	More...				about 12 years ago
Added copyright statement to readme file	Clifford Wolf	More...				about 12 years ago
Moved stand-alone libs to libs/ directory and added libs/subcircuit	Clifford Wolf	More...				about 12 years ago
Modify cost function to more aggressively absorb nets	Jason Luu	More...				about 12 years ago
More tuning to high fanout net handling	Jason Luu	More...				about 12 years ago
Special case code to consider high fanout nets in packing. For speed, we ignore high fanout nets when considering what blocks to place in a cluster, but when the number of feasible candidates is low, we should consider high fanout nets.	Jason Luu	More...				about 12 years ago
Remove unused function in power code	Jeffrey Goeders	More...				about 12 years ago
Added support for verilog genblock[index].member syntax	Clifford Wolf	More...				about 12 years ago
Update to power technology scripts.	Jeffrey Goeders	More...				about 12 years ago
Update technology files	Jeffrey Goeders	More...				about 12 years ago
Update technology files	Jeffrey Goeders	More...				about 12 years ago
Update power tasks and arches	Jeffrey Goeders	More...				about 12 years ago
Bug fix to power code	Jeffrey Goeders	More...				about 12 years ago
Merge pull request #2 from mschmoelzer/master	Clifford Wolf	More...				about 12 years ago
"fsm_export" pass: fix KISS file generation.	Martin Schmölzer	More...				about 12 years ago
partial work towards resolution of memory bug	Jason Luu	More...				about 12 years ago
use input API properly	Bert Vermeulen	More...				about 12 years ago
Add in new fracturable carry-chain architecture	Jason Luu	More...				about 12 years ago
Enable chains of LUTs. Eg. A->B->C	Jason Luu	More...				about 12 years ago
Added new files to complete previous commit.	Kons Na	More...				about 12 years ago
Added Odin II clock ratio support in the simulator, module view and additional exploration features to the visualization of Odin II.	Kons Na	More...				about 12 years ago
Bug during output logical equivalence, using too many opins because not able to reserve clb opins locally	Jason Luu	More...				about 12 years ago
Get VPR memory leak free. This change makes the default VPR flow completely memory leak free.	Jason Luu	More...				about 12 years ago
Must take into account corner case of multiple units connecting to same LUT	Jason Luu	More...				about 12 years ago
Change LUT logical equivalence representation from a complete bipartite graph to a star topology. This has two effects: 1) Enables us to now do molecules of LUTs. 2) More efficient both in memory and in speed	Jason Luu	More...				about 12 years ago
Change LUT logical equivalence representation from a complete bipartite graph to a star topology. This has two effects: 1) Enables us to now do molecules of LUTs. 2) More efficient both in memory and in speed	Jason Luu	More...				about 12 years ago
Update weekly regression test results	Jason Luu	More...				about 12 years ago
Reverting VPR Makefile	Jeffrey Goeders	More...				over 12 years ago
Update toggle-pin method of power estimation to include support for 'scale by factor'	Jeffrey Goeders	More...				over 12 years ago

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