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Analyzed 12 months ago. based on code collected about 3 years ago.

Commit Message	Contributor	Files Modified	Lines Added	Lines Removed	Code Location	Date
Mar 09, 2021 — Mar 09, 2022 Showing page 1,674 of 1,750 Search / Filter on:
Updates to clean up some rr_node highlighting code. Still doesn't highlight nets properly though.	Vaughn Betz	More...				about 12 years ago
test commit	Andre Pereira	More...				about 12 years ago
Fixed permissions bug in release gen script	Jason Luu	More...				about 12 years ago
Update golden results	Jason Luu	More...				about 12 years ago
Merge pull request #6 from hansiglaser/master	Clifford Wolf	More...				about 12 years ago
added option '-Dname[=definition]' to command 'read_verilog'	Johann Glaser	More...				about 12 years ago
memories and multipliers still broken but this update prevents a crash	Jason Luu	More...				about 12 years ago
reduced number of test cases in verilog writer reg test	Jason Luu	More...				about 12 years ago
fixed compiler warning	Jason Luu	More...				about 12 years ago
Post-synth netlist	Jason Luu	More...				about 12 years ago
code clean up	Mike Wang	More...				about 12 years ago
free_draw_structs	Mike Wang	More...				about 12 years ago
Removed test cases that have been moved to yosys-test.	Clifford Wolf	More...				about 12 years ago
Fixed to aggressive x-folding in opt_const	Clifford Wolf	More...				about 12 years ago
Power: Fix warnings & mem leak	Jeffrey Goeders	More...				about 12 years ago
Fixed bad indexing when looking up physical pin from logical net pin after place-and-route	Jason Luu	More...				about 12 years ago
Added SRC/power to the default include path for headers.	Vaughn Betz	More...				about 12 years ago
Merge branch 'master' of github.com:cliffordwolf/yosys	Clifford Wolf	More...				about 12 years ago
Merge branch 'bugfix'	Clifford Wolf	More...				about 12 years ago
Fixed synthesis of functions in latched blocks	Clifford Wolf	More...				about 12 years ago
Made release configuration use regular characters (multi-byte) not unicode. Enabled WIN32 graphics in the compile.	Vaughn Betz	More...				about 12 years ago
event_loop function call needs to pass four parameters in order to be compatible with the new graphics library	Mike Wang	More...				about 12 years ago
init_graphics function call needs to pass two parameters in order to be compatible with the new graphics library	Mike Wang	More...				about 12 years ago
Minor fixes to SDC section.	Vaughn Betz	More...				about 12 years ago
Fixed some Visual Studio warnings.	Vaughn Betz	More...				about 12 years ago
git-svn-id: https://vtr-verilog-to-routing.googlecode.com/svn/trunk@2128 8e3573b8-cf2c-4f14-ef6d-137439e28b8b	Mike Wang	More...				about 12 years ago
git-svn-id: https://vtr-verilog-to-routing.googlecode.com/svn/trunk@2127 8e3573b8-cf2c-4f14-ef6d-137439e28b8b	Mike Wang	More...				about 12 years ago
Added a pair of useful links to the new developer tutorial file.	Oleg Petelin	More...				about 12 years ago
Add vpr user manual to the docs	Jason Luu	More...				about 12 years ago
git-svn-id: https://vtr-verilog-to-routing.googlecode.com/svn/trunk@2124 8e3573b8-cf2c-4f14-ef6d-137439e28b8b	Jason Luu	More...				about 12 years ago

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